L. Pasini, P. Batude, J. Lacord, M. Cassé, B. Mathieu, B. Sklénard, F. P. Luce, J. Micout, A. Payet, F. Mazen, P. Besson, E. Ghegin, J. Borrel, R. Daubriac, L. Hutin, D. Blachier, D. Barge, S. Chhun, V. Mazzocchi, A. Cros, J. Barnes, Z. Saghi, V. Delaye, N. Rambal, V. Lapras, J. Mazurier, O. Weber, F. Andrieu, L. Brunet, C. Fenouillet-Béranger, Q. Rafhay, G. Ghibaudo, F. Cristiano, M. Haond, F. Boeuf, M. Vinet
{"title":"High performance CMOS FDSOI devices activated at low temperature","authors":"L. Pasini, P. Batude, J. Lacord, M. Cassé, B. Mathieu, B. Sklénard, F. P. Luce, J. Micout, A. Payet, F. Mazen, P. Besson, E. Ghegin, J. Borrel, R. Daubriac, L. Hutin, D. Blachier, D. Barge, S. Chhun, V. Mazzocchi, A. Cros, J. Barnes, Z. Saghi, V. Delaye, N. Rambal, V. Lapras, J. Mazurier, O. Weber, F. Andrieu, L. Brunet, C. Fenouillet-Béranger, Q. Rafhay, G. Ghibaudo, F. Cristiano, M. Haond, F. Boeuf, M. Vinet","doi":"10.1109/VLSIT.2016.7573407","DOIUrl":null,"url":null,"abstract":"3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573407","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).
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