R. Berthelon, F. Andrieu, E. Josse, R. Bingert, O. Weber, E. Serret, A. Aurand, S. DelMedico, V. Farys, C. Bernicot, E. Béchet, É. Bernard, T. Poiroux, D. Rideau, P. Scheer, E. Baylac, P. Perreau, M. Jaud, J. Lacord, E. Petitprez, A. Pofelski, S. Ortolland, P. Sardin, D. Dutartre, A. Claverie, M. Vinet, J. Marin, M. Haond
{"title":"14nm UTBB-FDSOI CMOS应变诱导布局效应的设计/技术协同优化:连续rx设计的实现和评估","authors":"R. Berthelon, F. Andrieu, E. Josse, R. Bingert, O. Weber, E. Serret, A. Aurand, S. DelMedico, V. Farys, C. Bernicot, E. Béchet, É. Bernard, T. Poiroux, D. Rideau, P. Scheer, E. Baylac, P. Perreau, M. Jaud, J. Lacord, E. Petitprez, A. Pofelski, S. Ortolland, P. Sardin, D. Dutartre, A. Claverie, M. Vinet, J. Marin, M. Haond","doi":"10.1109/VLSIT.2016.7573425","DOIUrl":null,"url":null,"abstract":"We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This effect is demonstrated by Nano-Beam Diffraction to be directly induced by the strain in the SiGe channel and reproduced by an accurate electrical compact model. An original continuous-RX design optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at VDD=0.8V supply voltage and a frequency gain up to 15% is simulated in a critical path of an A9 core.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"98 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Design / technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs\",\"authors\":\"R. Berthelon, F. Andrieu, E. Josse, R. Bingert, O. Weber, E. Serret, A. Aurand, S. DelMedico, V. Farys, C. Bernicot, E. Béchet, É. Bernard, T. Poiroux, D. Rideau, P. Scheer, E. Baylac, P. Perreau, M. Jaud, J. Lacord, E. Petitprez, A. Pofelski, S. Ortolland, P. Sardin, D. Dutartre, A. Claverie, M. Vinet, J. Marin, M. Haond\",\"doi\":\"10.1109/VLSIT.2016.7573425\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This effect is demonstrated by Nano-Beam Diffraction to be directly induced by the strain in the SiGe channel and reproduced by an accurate electrical compact model. An original continuous-RX design optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at VDD=0.8V supply voltage and a frequency gain up to 15% is simulated in a critical path of an A9 core.\",\"PeriodicalId\":129300,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Technology\",\"volume\":\"98 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2016.7573425\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573425","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design / technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs
We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This effect is demonstrated by Nano-Beam Diffraction to be directly induced by the strain in the SiGe channel and reproduced by an accurate electrical compact model. An original continuous-RX design optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at VDD=0.8V supply voltage and a frequency gain up to 15% is simulated in a critical path of an A9 core.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
