A. Bonnevialle, C. Le Royer, Y. Morand, S. Reboh, C. Plantier, N. Rambal, J.-P Pedini, S. Kerdilès, P. Besson, J. Hartmann, D. Marseilhan, B. Mathieu, R. Berthelon, M. Cassé, F. Andrieu, D. Rouchon, O. Weber, F. Boeuf, M. Haond, A. Claverie, M. Vinet
{"title":"为未来FDSOI一代提供高效双应变集成的智能解决方案","authors":"A. Bonnevialle, C. Le Royer, Y. Morand, S. Reboh, C. Plantier, N. Rambal, J.-P Pedini, S. Kerdilès, P. Besson, J. Hartmann, D. Marseilhan, B. Mathieu, R. Berthelon, M. Cassé, F. Andrieu, D. Rouchon, O. Weber, F. Boeuf, M. Haond, A. Claverie, M. Vinet","doi":"10.1109/VLSIT.2016.7573406","DOIUrl":null,"url":null,"abstract":"We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. “STRASS” and “BOX creep” techniques (for tensily and compressively stressed channels, respectively) are for the first time integrated in a localized manner on a state-of-the-art 14nm FDSOI route. STRASS enables to achieve +1.6 GPa in SOI active regions (w.r.t. +1.3 GPa for thin BOX sSOI). BOX creep process leads to more than +10% in hole mobility and +6% in Ieff(Ioff) plots. The BOX creep efficiency is investigated with respect to device dimensions: the electrical data evolution matches the proposed mobility model based on 2D simulated stress profiles.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Smart solutions for efficient dual strain integration for future FDSOI generations\",\"authors\":\"A. Bonnevialle, C. Le Royer, Y. Morand, S. Reboh, C. Plantier, N. Rambal, J.-P Pedini, S. Kerdilès, P. Besson, J. Hartmann, D. Marseilhan, B. Mathieu, R. Berthelon, M. Cassé, F. Andrieu, D. Rouchon, O. Weber, F. Boeuf, M. Haond, A. Claverie, M. Vinet\",\"doi\":\"10.1109/VLSIT.2016.7573406\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. “STRASS” and “BOX creep” techniques (for tensily and compressively stressed channels, respectively) are for the first time integrated in a localized manner on a state-of-the-art 14nm FDSOI route. STRASS enables to achieve +1.6 GPa in SOI active regions (w.r.t. +1.3 GPa for thin BOX sSOI). BOX creep process leads to more than +10% in hole mobility and +6% in Ieff(Ioff) plots. The BOX creep efficiency is investigated with respect to device dimensions: the electrical data evolution matches the proposed mobility model based on 2D simulated stress profiles.\",\"PeriodicalId\":129300,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Technology\",\"volume\":\"76 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2016.7573406\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573406","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Smart solutions for efficient dual strain integration for future FDSOI generations
We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. “STRASS” and “BOX creep” techniques (for tensily and compressively stressed channels, respectively) are for the first time integrated in a localized manner on a state-of-the-art 14nm FDSOI route. STRASS enables to achieve +1.6 GPa in SOI active regions (w.r.t. +1.3 GPa for thin BOX sSOI). BOX creep process leads to more than +10% in hole mobility and +6% in Ieff(Ioff) plots. The BOX creep efficiency is investigated with respect to device dimensions: the electrical data evolution matches the proposed mobility model based on 2D simulated stress profiles.
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