Circuit performance analysis of negative capacitance FinFETs

Abstract

Circuit-level performance analysis of negative capacitance FinFETs (NC-FinFET) is presented for ultra-low power high performance applications. Circuit simulations are performed by developing a compact model which solves Landau-Khalatnikov (L-K) equations self-consistently with the three-dimensional device electrostatics of the FinFET device. Using an accurate Lg = 30 nm FinFET model, L-K model parameters of ferroelectric (FE) layer are extracted from an experimental NC-FinFET data. With the experimentally calibrated model, we show for the first time that for the same inverter delay as the 14 nm ITRS FinFET, Vdd for NC-FinFET can be lowered from 0.7 V to 0.25 V, reducing energy by ~10×. Optimization of the FE layer parameters can further boost the device performance.