高宽高比InGaAs finfet,翅片宽度低于20nm

A. Vardi, Jianqiang Lin, Wenjie Lu, Xin Zhao, J. D. del Alamo
{"title":"高宽高比InGaAs finfet,翅片宽度低于20nm","authors":"A. Vardi, Jianqiang Lin, Wenjie Lu, Xin Zhao, J. D. del Alamo","doi":"10.1109/VLSIT.2016.7573408","DOIUrl":null,"url":null,"abstract":"We demonstrate self-aligned InGaAs FinFETs with sub-20 nm fin width fabricated through a CMOS compatible front-end process. Working devices with fins as narrow as 7 nm, fin aspect ratios in excess of 5 and gate lengths as short as 20 nm have been fabricated using precision dry etching and digital etch. The devices also feature self-aligned metal contacts that are 20-30 nm away from the edge of the gate. FinFETs with Lg=30 nm, Wf=22 nm and channel height of 40 nm exhibit a transconductance of 1400 μS/μm at VDS=0.5 V. When normalized to Wf, this is a record value among all III-V FinFETs, indicating that our device architecture makes efficient use of conduction along the fin sidewalls.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"High aspect ratio InGaAs FinFETs with sub-20 nm fin width\",\"authors\":\"A. Vardi, Jianqiang Lin, Wenjie Lu, Xin Zhao, J. D. del Alamo\",\"doi\":\"10.1109/VLSIT.2016.7573408\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate self-aligned InGaAs FinFETs with sub-20 nm fin width fabricated through a CMOS compatible front-end process. Working devices with fins as narrow as 7 nm, fin aspect ratios in excess of 5 and gate lengths as short as 20 nm have been fabricated using precision dry etching and digital etch. The devices also feature self-aligned metal contacts that are 20-30 nm away from the edge of the gate. FinFETs with Lg=30 nm, Wf=22 nm and channel height of 40 nm exhibit a transconductance of 1400 μS/μm at VDS=0.5 V. When normalized to Wf, this is a record value among all III-V FinFETs, indicating that our device architecture makes efficient use of conduction along the fin sidewalls.\",\"PeriodicalId\":129300,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Technology\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2016.7573408\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573408","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

摘要

我们展示了自对准InGaAs finfet,其片宽低于20 nm,通过CMOS兼容的前端工艺制造。利用精密干式蚀刻和数字蚀刻技术,已经制造出了翅片窄至7纳米、翅片宽高比超过5、栅极长度短至20纳米的工作装置。该器件还具有自对准金属触点,距离栅极边缘20-30纳米。Lg=30 nm, Wf=22 nm,通道高度为40 nm的finfet在VDS=0.5 V时的跨导率为1400 μS/μm。当归一化为Wf时,这是所有III-V型finfet中的记录值,表明我们的器件架构有效地利用了沿翅片侧壁的传导。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High aspect ratio InGaAs FinFETs with sub-20 nm fin width
We demonstrate self-aligned InGaAs FinFETs with sub-20 nm fin width fabricated through a CMOS compatible front-end process. Working devices with fins as narrow as 7 nm, fin aspect ratios in excess of 5 and gate lengths as short as 20 nm have been fabricated using precision dry etching and digital etch. The devices also feature self-aligned metal contacts that are 20-30 nm away from the edge of the gate. FinFETs with Lg=30 nm, Wf=22 nm and channel height of 40 nm exhibit a transconductance of 1400 μS/μm at VDS=0.5 V. When normalized to Wf, this is a record value among all III-V FinFETs, indicating that our device architecture makes efficient use of conduction along the fin sidewalls.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信