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2006 IEEE International Conference on IC Design and Technology最新文献

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Evaluation of a Non-Volatile FPGA based on MRAM technology 基于MRAM技术的非易失性FPGA的评估
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220782
W. Zhao, E. Belhaire, V. Javerliac, C. Chappert, B. Dieny
{"title":"Evaluation of a Non-Volatile FPGA based on MRAM technology","authors":"W. Zhao, E. Belhaire, V. Javerliac, C. Chappert, B. Dieny","doi":"10.1109/ICICDT.2006.220782","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220782","url":null,"abstract":"In this paper, we propose a new structure of FPGA based on MRAM technology; we name it MFPGA (magnetic FPGA). FPGA based on SRAM technology has been developed in the last years, because of its high speed and near limitless number of reprogramming, however SRAM is volatile thereby the configuration information and the intermediate data will be lost when power is turned off. By using MTJs (magnetic tunnel junction) as the storage elements of FPGA, we can realize the non-volatility of FPGA, and then we will not need the external memory. In our simulation, the start-up time of circuit can be decreased up to some hundred pico seconds. Except for the rapid start-up time, we can also configure the algorithm and logic function of the FPGA circuit very simply and rapidly. The other advantage of using MRAM technology is that we will not enlarge the circuit surface, because the storage element MTJs are on the semiconductor surface","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"10 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122904579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Inductance Modeling for On-chip interconnects using Elevated coplanar waveguide 采用高架共面波导的片上互连电感建模
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220825
R. Ranjithkumar, S. Rajaram, S. Raju, V. Abhaikumar
{"title":"Inductance Modeling for On-chip interconnects using Elevated coplanar waveguide","authors":"R. Ranjithkumar, S. Rajaram, S. Raju, V. Abhaikumar","doi":"10.1109/ICICDT.2006.220825","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220825","url":null,"abstract":"As technology advances into the very deep submicron era, the operating frequencies are fast reaching the vicinity of several gigahertz and switching times are getting to the sub nanosecond levels. The ever increasing quest for high speed applications highlighted the previously negligible inductive effects of interconnects, such as signal delay, over shoot, and crosstalk as stated in R. Achar and M. S. Nakhla (2001). At gigahertz frequencies, long interconnect wires exhibit transmission line behavior. This paper describes the inductive effects of on-chip interconnects using elevated coplanar waveguide structure as a transmission line for multilayer chip. It uses realistic test structures that study the inductive effect of local interconnects to typical power and ground grids. Electrical equivalent modeling for ECPW was derived using complex image method. ECPW structure was designed for 10GHz and simulated in Ansoft HFSS V9.2.1. ECPW structure shows an insertion loss of 0.02 dB and return loss of -23 dB. Also shows the inductive reactance dominates the resistance at higher frequencies","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124354828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Charging Damage and Product Impact in a Bulk CMOS Technology 批量CMOS技术中的充电损伤与产品影响
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220805
T. Hook, C. Musante, D. Harmon, T. Sullivan
{"title":"Charging Damage and Product Impact in a Bulk CMOS Technology","authors":"T. Hook, C. Musante, D. Harmon, T. Sullivan","doi":"10.1109/ICICDT.2006.220805","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220805","url":null,"abstract":"In this paper, we tabulate the characteristics of antennas in several real designs in a 180-nm technology, and show data indicating that the product is not as susceptible to charging damage as the test structures used to control the process line. The experiment consisted of evaluating a large (500 pieces) sample of parts with considerable process-induced antenna damage - and yet no measurable degradation in product performance, yield, or reliability was found","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122061222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Pushing the scaling limits of embedded non-volatile memories with high-K materials 突破高k材料嵌入式非易失性存储器的缩放极限
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220786
M. van Duuren, R. van Schaijk, M. Slotboom, P. Tello, N. Akil, A. H. Miranda, D. Golubović
{"title":"Pushing the scaling limits of embedded non-volatile memories with high-K materials","authors":"M. van Duuren, R. van Schaijk, M. Slotboom, P. Tello, N. Akil, A. H. Miranda, D. Golubović","doi":"10.1109/ICICDT.2006.220786","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220786","url":null,"abstract":"In this paper, two alternative cell concepts to overcome these issues were discussed: conventional floating gate cells with high-K inter-poly dielectrics (IPD) and nitride trapping devices with high-K materials. In both concepts, the reduced equivalent oxide thickness (EOT) of the high-K layers helps reducing VPE, whereas the low leakage current ensures a good data retention. In this work, only hafnium based high-K materials were used: hafnium oxide (HfO2) and nitrided hafnium silicate (HfSiON), both deposited by MOCVD. The choice for these materials was based on their expected availability in the sub-45nm CMOS nodes","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125526535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Reliability of Ultra Thin Gate Oxide CMOS Devices: Design Perspective 超薄栅极氧化物CMOS器件的可靠性:设计视角
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220808
C. Parthasarathy, M. Denais, V. Huard, G. Ribes, E. Vincent, A. Bravaix
{"title":"Reliability of Ultra Thin Gate Oxide CMOS Devices: Design Perspective","authors":"C. Parthasarathy, M. Denais, V. Huard, G. Ribes, E. Vincent, A. Bravaix","doi":"10.1109/ICICDT.2006.220808","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220808","url":null,"abstract":"Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper discusses degradation due to channel hot carriers, NBTI and oxide breakdown from a design perspective - in terms of characterization, mechanisms and circuit analysis - introducing assessment of multiple degradation modes on same device","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126739789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simulation of patterning-induced circuit performance variability 图形诱导电路性能变异性的仿真
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220827
A. Nackaerts, S. Verhaegen, J. Ramos, G. Vandenberghe, S. Biesemans
{"title":"Simulation of patterning-induced circuit performance variability","authors":"A. Nackaerts, S. Verhaegen, J. Ramos, G. Vandenberghe, S. Biesemans","doi":"10.1109/ICICDT.2006.220827","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220827","url":null,"abstract":"In this paper the interactions between layout, lithography, and circuit performance variability are studied by simulating Monte-Carlo layout variations of circuits","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129152492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Re-examination of Deuterium Effect on Negative Bias Temperature Instability in Ultra-thin Gate Oxides 氘对超薄栅极氧化物负偏置温度不稳定性影响的再检验
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220806
Y. Mitani, H. Satake
{"title":"Re-examination of Deuterium Effect on Negative Bias Temperature Instability in Ultra-thin Gate Oxides","authors":"Y. Mitani, H. Satake","doi":"10.1109/ICICDT.2006.220806","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220806","url":null,"abstract":"In this work, the effect of deuterium on negative bias temperature instability (NBTI) was investigated using p+-gate and n+ -gate/pMOSFETs. As a result, it was found that the elimination of interface-trap generation by deuterium incorporation is observed in the case of n+-gate/pMOSFETs, while no isotope effect is observed in p+-gate/pMOSFETs. The correlation between energy of injected carrier and interface trap generation was investigated based on the impact ionization probability. In the case of p+-gate/pMOSFETs, the interaction between Si-H bonds and holes in the inversion layer seems to be responsible for hydrogen release from SiO2/Si interface. On the other hand, in the case of n+-gate/pMOSFETs, injecting energetic electrons from gate electrodes break Si-H bonds. Namely, it can be concluded that two processes of Si-H bond breaking relate to interface trap generation under NBT stress","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127892243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of Advanced SOI Substrates on Device Architecture and Design 先进SOI基板对器件架构和设计的影响
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220815
C. Mazure, J. Wasselin
{"title":"Impact of Advanced SOI Substrates on Device Architecture and Design","authors":"C. Mazure, J. Wasselin","doi":"10.1109/ICICDT.2006.220815","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220815","url":null,"abstract":"The engineering of SOI substrates has allowed for optimization of MOSFET performance while minimizing leakage and parasitic elements. Design innovations have amplified the SOI benefits with a significant reduction of the cost of ownership. To move beyond the 90nm IC node, mobility enhancing strain techniques have been added to the CMOS process. While strained silicon on insulator appears to be a solution for reducing power consumption without affecting the device performance, SOI on high resistivity substrates offers a solution tailored to RF applications. An overview of the advances in Smart Cuttrade engineered substrates will be given, and their impact on device design will be discussed","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128247395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A scalable Stacked Gate NOR/NAND Flash Technology compatible with high-k and metal gates for sub 45nm generations 一种可扩展的堆叠栅NOR/NAND闪存技术，兼容45纳米以下的高k栅极和金属栅极
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220783
J. de Vos, L. Haspeslagh, M. Demand, K. Devriendt, D. Wellekens, S. Beckx, J. V. Houdt
{"title":"A scalable Stacked Gate NOR/NAND Flash Technology compatible with high-k and metal gates for sub 45nm generations","authors":"J. de Vos, L. Haspeslagh, M. Demand, K. Devriendt, D. Wellekens, S. Beckx, J. V. Houdt","doi":"10.1109/ICICDT.2006.220783","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220783","url":null,"abstract":"In this paper a scalable stacked gate technology with self-aligned floating gate (FG) is presented. It can be used for both NOR and NAND flash architectures. By introducing high-k materials for the interpoly dielectric (IPD) a planar structure can be used, which allows a much denser structure. It is also shown that the planar structure of the memory cell facilitates the introduction of metal gates. The successful integration of a 110nm stacked gate transistor with high-k IPD and TiN metal gate is illustrated","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121147603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Reviews and Prospects of Nanoscale SRAMs 纳米sram的研究进展与展望
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220835
K. Osada
{"title":"Reviews and Prospects of Nanoscale SRAMs","authors":"K. Osada","doi":"10.1109/ICICDT.2006.220835","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220835","url":null,"abstract":"Designing 6-T SRAM cells is becoming more difficult as devices are scaled down and VDD is reduced. This paper describes soft error, the standby current, and the static noise margin for the low-voltage designs that must be carefully considered. First, cosmic-ray-induced multicell errors, which have now become a serious problem, are investigated. A new circuit architecture is proposed for the handling of cosmic-ray-induced multicell errors. Next, recent developments to suppress tunnel leakage currents for low-retention-current SRAMs are presented. Finally, future prospects of SRAM cells are discussed in terms of low-voltage designs. We propose a new SRAM cell using a new MOSFET on an ultra-thin BOX","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128874531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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