C. Parthasarathy, M. Denais, V. Huard, G. Ribes, E. Vincent, A. Bravaix
{"title":"超薄栅极氧化物CMOS器件的可靠性:设计视角","authors":"C. Parthasarathy, M. Denais, V. Huard, G. Ribes, E. Vincent, A. Bravaix","doi":"10.1109/ICICDT.2006.220808","DOIUrl":null,"url":null,"abstract":"Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper discusses degradation due to channel hot carriers, NBTI and oxide breakdown from a design perspective - in terms of characterization, mechanisms and circuit analysis - introducing assessment of multiple degradation modes on same device","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"170 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Reliability of Ultra Thin Gate Oxide CMOS Devices: Design Perspective\",\"authors\":\"C. Parthasarathy, M. Denais, V. Huard, G. Ribes, E. Vincent, A. Bravaix\",\"doi\":\"10.1109/ICICDT.2006.220808\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper discusses degradation due to channel hot carriers, NBTI and oxide breakdown from a design perspective - in terms of characterization, mechanisms and circuit analysis - introducing assessment of multiple degradation modes on same device\",\"PeriodicalId\":447050,\"journal\":{\"name\":\"2006 IEEE International Conference on IC Design and Technology\",\"volume\":\"170 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-08-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Conference on IC Design and Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2006.220808\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Conference on IC Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2006.220808","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reliability of Ultra Thin Gate Oxide CMOS Devices: Design Perspective
Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper discusses degradation due to channel hot carriers, NBTI and oxide breakdown from a design perspective - in terms of characterization, mechanisms and circuit analysis - introducing assessment of multiple degradation modes on same device