2006 IEEE International Conference on IC Design and Technology最新文献

Delay and Power Monitoring Scheme for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control 通过电源和阈值电压控制实现最小功耗的延迟和功率监测方案

2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220832

M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, Y. Hagihara

引用次数: 0

Leakage Power Reduction Techniques applied to 90-nm SoC Application Processor 90纳米SoC应用处理器的泄漏功耗降低技术

2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220781

P. Royannez, H. Mair, F. Dahan, M. Wagner, M. Streeter, L. Bouetel, J. Blasquez, H. Clasen, G. Semino, J. Dong, D. Scott, B. Pitts, C. Raibaut, U. Ko

引用次数: 1

Highly Manufacturable Single-Bridge-Channel MOSFET (SBCFET) 高度可制造的单桥通道MOSFET (SBCFET)

2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220811

S. Lee, Min-Sang Kim, E. Yoon, Sung-min Kim, Lian Jun, Dong-Won Kim, Donggun Park

引用次数: 3

A Novel FDSOI MOSFET with Block Oxide Enclosed Body 一种新型块氧化封闭体FDSOI MOSFET

2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220813

Jyi-Tsong Lin, Y. Eng, Kuo-Dong Huang, Tai-Yi Lee, Kao-Cheng Lin

{"title":"A Novel FDSOI MOSFET with Block Oxide Enclosed Body","authors":"Jyi-Tsong Lin, Y. Eng, Kuo-Dong Huang, Tai-Yi Lee, Kao-Cheng Lin","doi":"10.1109/ICICDT.2006.220813","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220813","url":null,"abstract":"In this paper, we propose a novel fully depleted silicon-on-insulator MOSFET with block oxide enclosed body (bFDSOI). To differ with the conventional FDSOI MOSFET, the proposed SOI structure shows enhanced performance by exploiting sidewall spacer process. For this new bFDSOI device, the electric field between the body and the source/drain (S/D) region is restrained by the block oxide resulting in that the ultra-short-channel effects (USCEs) are suppressed. Thus, the simulation results of bFDSOI exhibit reduced drain-induced barrier lowering (DIBL), excellent subthreshold swing (SS), good roll-off characteristics and high drain output resistance for 40 nm thick enough body. In order to eliminate the floating-body problem, the bFDSOI device must not be operated under the partially depleted (PD) regime. Although this is the limit of device design, as the gate length is scaled down, the requirement of the ultra-thin body (UTB) structure is not needed to maintain its ultra-short-channel characteristics control over the channel due to the block oxide serves as isolation between the body and the S/D region. Moreover, owing to that the sufficient thick body is used; the bFDSOI device results in good amelioration of self-heating effects (SHEs), which is very important in a nano-scale SOI MOSFET design","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123933020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A Novel DCVS Tree Reduction Algorithm 一种新的DCVS树约简算法

2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220824

O. Kavehie, K. Navi, T. Nikoubin, M. Rouholamini

引用次数: 9

Carbon Nanotubes for Potential Device and Interconnect Applications 潜在器件和互连应用的碳纳米管

2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220814

W. Hoenlein

引用次数: 6

Industry Trend: Planar Double Gate Technology 行业趋势:平面双栅技术

2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220799

T. Dao, P. A. Montgomery, E. Luckowski, J. John, J. Norbert, S. Stewart, B. Nguyen, J. Teplik

{"title":"Industry Trend: Planar Double Gate Technology","authors":"T. Dao, P. A. Montgomery, E. Luckowski, J. John, J. Norbert, S. Stewart, B. Nguyen, J. Teplik","doi":"10.1109/ICICDT.2006.220799","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220799","url":null,"abstract":"Double gate FDSOI device performance improvements over single gate devices have been well documented by many companies in the semiconductor industry, having almost double the drive current, close to ideal subthreshold slope, reduced SCE, and reduced DIBL. However, in the past five years, planar double gate technology has been largely ignored, except for the case of IBM, because of the manufacturing challenges. These include the construction of the bottom gate underneath the FET body, the alignment of the bottom gate to the top gate, and the difficult task of incorporating metal gate or high k dielectric material for the bottom gate formation. From the design and device physics point of view, the planar double gate structure is predicted to behave similarly to single gate with the additional flexibility that the planar double-gate approach allows one to reach the limiting body thickness. In the past year, there has been significant renewed interest based on the increase in reports published by semiconductor companies, research labs and universities on the planar double gate manufacturing process. In this paper, an in-depth analysis will be done to compare industry planar double gate manufacturing methods, including that of Freescale Semiconductor","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133470107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Modified Force-Directed Scheduling for Peak and Average Power Optimization using Multiple Supply-Voltages 基于多电源电压的峰值和平均功率优化的改进力定向调度

2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220823

Atef Allam, J. Ramanujam

引用次数: 12

Circuits and design techniques for secure ICs resistant to side-channel attacks 抗侧信道攻击的安全集成电路和设计技术

2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220791

I. Verbauwhede, K. Tiri, D. Hwang, P. Schaumonr

{"title":"Circuits and design techniques for secure ICs resistant to side-channel attacks","authors":"I. Verbauwhede, K. Tiri, D. Hwang, P. Schaumonr","doi":"10.1109/ICICDT.2006.220791","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220791","url":null,"abstract":"Integrated circuits used for security applications, such as smart-cards, leak information. The key or other sensitive information can be guessed by monitoring the execution time, the power variation and/or the electromagnetic radiation of the integrated circuit. This class of so-called side-channel attacks doesn't need expensive equipment or intrusive monitoring to be effective. We have shown that we can obtain the secret key out of a regular standard CMOS implementation of the AES encryption algorithm by monitoring the power consumption of only 2000 encryptions. This is orders of magnitude lower than the mathematical security of 2128 possible encryption keys to break the algorithm. The root cause of this problem is that standard CMOS is power efficient and it will only consume dynamic power when nodes are switching. Mathematical solutions have been proposed that include randomization and masking techniques. Our original approach is that we address the problem at circuit level. Instead of a full custom layout, a few key modifications are incorporated in a regular synchronous CMOS standard cell design flow. We present the basis for side-channel attack resistance and adjust the library databases and constraint files of the synthesis and place & route procedures. We show the measurement results on two functionally identical co-processors which were fabricated using a TSMC 6M 0.18mum CMOS. We also discuss issues of side-channel resistance when implementing ICs in future technologies","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129719367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Leakage Reduction at Architectural Level 在架构层面减少泄漏

2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220780

C. Piguet, C. Schuster, Jean-Luc Nagel

引用次数: 1