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2006 IEEE International Conference on IC Design and Technology最新文献

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High Speed, Small Area, Reliable, LTPS TFT-based Level Shifter for System-On-Panel Technology 高速，小面积，可靠，基于LTPS tft的板上系统电平转换器
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220795
J.C. Lee, J.Y. Jeong
{"title":"High Speed, Small Area, Reliable, LTPS TFT-based Level Shifter for System-On-Panel Technology","authors":"J.C. Lee, J.Y. Jeong","doi":"10.1109/ICICDT.2006.220795","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220795","url":null,"abstract":"Due to poor mobility, coarse design rule, and poor parameter uniformity, improvement in design methodology becomes critical in the TFT-based system-on-panel design. We present a new TFT based inverting level shifter which has been optimized for LTPS TFT properties for superior characteristics. Compared to a power hungry, high speed offset voltage type level shifter, the proposed circuit reached the same speed with only 10% power and 51% real estate. We have fabricated and tested the circuit with 4 micron LTPS TFT technology","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132055673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Improved Linearity Active Resistor with Controllable Negative Resistance 具有可控负电阻的改进线性有源电阻
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220794
C. Popa
{"title":"Improved Linearity Active Resistor with Controllable Negative Resistance","authors":"C. Popa","doi":"10.1109/ICICDT.2006.220794","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220794","url":null,"abstract":"An original active resistor circuit is further presented. The main advantages of the new proposed implementations are the improved linearity, the small area consumption and the improved frequency response. An original technique for linearizing the I(V) characteristic of the active resistor will be proposed, based on the utilization of a new linear differential amplifier and on a current-pass circuit. The errors introduced by the second-order effects will be strongly reduced, while the circuit frequency response of the circuit is very good as a result of operating all MOS transistors in the saturation region. In order to design a circuit having a negative equivalent resistance, an original method specific to the proposed implementation of the active resistor circuit will be presented. The circuit is implemented in 035mum CMOS technology, the SPICE simulation confirming the theoretical estimated results and showing a linearity error less than 0.5 % for an extended input range (plusmn500mV) and a small value of the supply voltage (plusmn3.3V)","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127036209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Characterization of HfSiON Gate Dielectric with TiN Gate on Multi-Gate MOSFET 多栅极MOSFET上TiN栅极的HfSiON栅极介电特性
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-05-01 DOI: 10.1109/ICICDT.2006.220810
W. Xiong, C. Young, K. Matthew, C. Rinn Cleavelin, T. Schulz, K. Schruefer, P. Patruno
{"title":"Characterization of HfSiON Gate Dielectric with TiN Gate on Multi-Gate MOSFET","authors":"W. Xiong, C. Young, K. Matthew, C. Rinn Cleavelin, T. Schulz, K. Schruefer, P. Patruno","doi":"10.1109/ICICDT.2006.220810","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220810","url":null,"abstract":"The hysteresis and mobilities of 1nm EOT HfSiON dielectric on multi-gate MOSFET (MuGFET) with TiN metal gate were studied. We did not observe any drain current hysteresis. This is consistent with the same gate stack on planar bulk MOSFET. However, we found significant electron and hole mobility degradation for MuGFET compared to SiO2 control devices (up to -25%). The percentage of degradation is higher than the same gate stack on planar bulk MOSFET, which points to the poor interfacial oxide quality on the MuGFET fin sidewalls","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127595982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Assessment of Process-Induced Damage in High-κ Transistors 高-&#954工艺损伤评估晶体管
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-05-01 DOI: 10.1109/ICICDT.2006.220802
C. Young, R. Choi, D. Heh, A. Neugroschel, Hokyung Park, C. Kang, G.A. Brown, S. Song, B. Lee, G. Bersuker
{"title":"Assessment of Process-Induced Damage in High-κ Transistors","authors":"C. Young, R. Choi, D. Heh, A. Neugroschel, Hokyung Park, C. Kang, G.A. Brown, S. Song, B. Lee, G. Bersuker","doi":"10.1109/ICICDT.2006.220802","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220802","url":null,"abstract":"Using a combination of electrical characterization techniques, one can separate contributions from generated and pre-existing electron traps inherent to high-k dielectrics, as well as identify process-induced effects in the device characteristics","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126950311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interpoly Oxide Related Fast Bit Failures in the Himos™ Flash Memory Cell Himos&#8482中与氧化物插值相关的快速位失效闪存单元
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-05-01 DOI: 10.1109/ICICDT.2006.220784
J. Ackaert, T. Yao, A. Lowe, P. Gassot, W. Ooghe, L. Schlegel, P. Bogaert, H. Branquart
{"title":"Interpoly Oxide Related Fast Bit Failures in the Himos™ Flash Memory Cell","authors":"J. Ackaert, T. Yao, A. Lowe, P. Gassot, W. Ooghe, L. Schlegel, P. Bogaert, H. Branquart","doi":"10.1109/ICICDT.2006.220784","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220784","url":null,"abstract":"A new data retention failure of the HIMOStrade cell is shown in this paper. The characterization of the failing bit reveals several differences with usual moving bits: the floating gate charge leaks through the interpoly dielectric. Investigations on the process suggest local damage of the interpoly oxide due to exposure to the erase junction implant. The issue is caused by notching of the erase junction implant mask allowing this implant to degrade the interpoly oxide. The issue is solved by the introduction of a bottom anti reflective coating layer, preventing this notching resulting is a significant increase of the yield and the processing window","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132635490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the Recovery of Simulated Plasma Process Induced Damage in High-κ Dielectrics 高温模拟等离子体过程损伤的修复研究电介质
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-05-01 DOI: 10.1109/ICICDT.2006.220803
L. Pantisano, B. O 'sullivan, P. Roussel, R. Degraeve, G. Groeseneken, S. Degendt, M. Heyns
{"title":"On the Recovery of Simulated Plasma Process Induced Damage in High-&#954; Dielectrics","authors":"L. Pantisano, B. O 'sullivan, P. Roussel, R. Degraeve, G. Groeseneken, S. Degendt, M. Heyns","doi":"10.1109/ICICDT.2006.220803","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220803","url":null,"abstract":"A detailed analysis of the ability of high-k materials to recover from plasma damage, as simulated by Fowler-Nordheim stress is presented. Forming gas and high temperature rapid thermal anneal (RTA) steps are compared to determine their efficiency at trap recovery. The annealing responses of the technologically relevant HfSiON and HfO2 materials (EOT<2nm) are correlated with structural differences in these dielectrics, as well as the trap generation rate, centroids and defect de-passivation. We show that plasma damage can be successfully recovered for HfO2 by high temperature annealing","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126799884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Silicon characterization of standby leakage reduction techniques in a 0.13μm Low Power Partially-Depleted Silicon-On-Insulator Technology 0.13&#956;m低功耗部分耗尽绝缘体上硅技术中待机泄漏减少技术的硅特性
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-05-01 DOI: 10.1109/ICICDT.2006.220779
N. L'Hostis, O. Thomas, S. Haendler, A. Amara, P. Flatresse, M. Belleville
{"title":"Silicon characterization of standby leakage reduction techniques in a 0.13&#956;m Low Power Partially-Depleted Silicon-On-Insulator Technology","authors":"N. L'Hostis, O. Thomas, S. Haendler, A. Amara, P. Flatresse, M. Belleville","doi":"10.1109/ICICDT.2006.220779","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220779","url":null,"abstract":"This paper presents silicon characterization results of various power gating techniques in a 0.13mum low power PD-SOI technology. A standby leakage current comparison is performed for floating body, body contacted and DTMOS transistors. It is shown that sleep transistors composed of PMOS in DTMOS configuration with an increased channel length are the best devices to reduce leakage power consumption in standby mode. Furthermore, on one hand, SOI helps reducing dynamic power consumption by more than 40% compared to bulk, and on the other hand, by implementing leakage reduction techniques, the standby leakage power is lowered by one decade","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126251449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Accurate Circuit Performance Prediction Model and Lifetime Prediction Method of NBT Stressed Devices for Highly Reliable ULSI Circuits 高可靠ULSI电路中NBT应力器件的精确电路性能预测模型及寿命预测方法
2006 IEEE International Conference on IC Design and Technology Pub Date : 1900-01-01 DOI: 10.1109/iedm.2005.1609448
R. Kuroda, K. Watanabe, A. Teramoto, M. Mifuji, T. Yamaha, S. Sugawa, T. Ohmi
{"title":"Accurate Circuit Performance Prediction Model and Lifetime Prediction Method of NBT Stressed Devices for Highly Reliable ULSI Circuits","authors":"R. Kuroda, K. Watanabe, A. Teramoto, M. Mifuji, T. Yamaha, S. Sugawa, T. Ohmi","doi":"10.1109/iedm.2005.1609448","DOIUrl":"https://doi.org/10.1109/iedm.2005.1609448","url":null,"abstract":"An accurate circuit level prediction model for predicting performance degradation due to negative bias temperature (NBT) stress and a device lifetime prediction method are proposed in this paper. The proposed model consists of a threshold voltage (Vth) shift and a drain current (ID) reduction models. The developed models are incorporated into a compact MOSFET model so that we can directly link the device electrical degradation to the circuit simulation. The validity of the developed models is confirmed by the experimental results of I-V characteristics of pMOSFET before and after stress. Then, the circuit performance prediction is carried out for a 199-stage ring oscillator on its waveform and oscillation frequency. Excellent agreements between experimental results and predicted results are obtained. Since only a suitable acceleration method allows us to develop the accurate models, the new negative bias temperature instability (NBTI) acceleration method using cold-holes is also developed. Finally, we demonstrate the accurate NBTI lifetime prediction using the method","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129305509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Flash memory: a challenged memory technology 闪存:一种具有挑战性的存储技术
2006 IEEE International Conference on IC Design and Technology Pub Date : 1900-01-01 DOI: 10.1109/icicdt.2006.1669374
J. van Houdt
{"title":"Flash memory: a challenged memory technology","authors":"J. van Houdt","doi":"10.1109/icicdt.2006.1669374","DOIUrl":"https://doi.org/10.1109/icicdt.2006.1669374","url":null,"abstract":"Flash memory although being an evolutionary rather than revolutionary technology nevertheless revolutionized the entire memory business. While (electrically) erasable and programmable ROMs (EEPROMs and EPROMs) only served a minor application field, the combination of electrical erasability with high density - known today as flash memory - has changed the face of the memory business in an unprecedented way. Although the technology is constantly being challenged by new promising alternatives, there is still quite some momentum remaining for flash scaling provided the technology becomes more application-specific and more hierarchically integrated with other memories on the system level. This paper briefly reviews the basics of NOR and NAND technology as well as its embedded counterparts as being used today, the way they are linked to the application and system levels, as well as some alternative charge-based memories such as nanocrystal and nitride memory","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129428848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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