R. Kuroda, K. Watanabe, A. Teramoto, M. Mifuji, T. Yamaha, S. Sugawa, T. Ohmi
{"title":"Accurate Circuit Performance Prediction Model and Lifetime Prediction Method of NBT Stressed Devices for Highly Reliable ULSI Circuits","authors":"R. Kuroda, K. Watanabe, A. Teramoto, M. Mifuji, T. Yamaha, S. Sugawa, T. Ohmi","doi":"10.1109/iedm.2005.1609448","DOIUrl":null,"url":null,"abstract":"An accurate circuit level prediction model for predicting performance degradation due to negative bias temperature (NBT) stress and a device lifetime prediction method are proposed in this paper. The proposed model consists of a threshold voltage (Vth) shift and a drain current (ID) reduction models. The developed models are incorporated into a compact MOSFET model so that we can directly link the device electrical degradation to the circuit simulation. The validity of the developed models is confirmed by the experimental results of I-V characteristics of pMOSFET before and after stress. Then, the circuit performance prediction is carried out for a 199-stage ring oscillator on its waveform and oscillation frequency. Excellent agreements between experimental results and predicted results are obtained. Since only a suitable acceleration method allows us to develop the accurate models, the new negative bias temperature instability (NBTI) acceleration method using cold-holes is also developed. Finally, we demonstrate the accurate NBTI lifetime prediction using the method","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Conference on IC Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/iedm.2005.1609448","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
An accurate circuit level prediction model for predicting performance degradation due to negative bias temperature (NBT) stress and a device lifetime prediction method are proposed in this paper. The proposed model consists of a threshold voltage (Vth) shift and a drain current (ID) reduction models. The developed models are incorporated into a compact MOSFET model so that we can directly link the device electrical degradation to the circuit simulation. The validity of the developed models is confirmed by the experimental results of I-V characteristics of pMOSFET before and after stress. Then, the circuit performance prediction is carried out for a 199-stage ring oscillator on its waveform and oscillation frequency. Excellent agreements between experimental results and predicted results are obtained. Since only a suitable acceleration method allows us to develop the accurate models, the new negative bias temperature instability (NBTI) acceleration method using cold-holes is also developed. Finally, we demonstrate the accurate NBTI lifetime prediction using the method