发布求助
文献互助 智能选刊 最新文献

2006 IEEE International Conference on IC Design and Technology最新文献

筛选
英文 中文
Evaluation of the robustness of dual rail logic against DPA 双轨逻辑对DPA的鲁棒性评价
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220792
A. Razafindraibe, P. Maurine, M. Robert
{"title":"Evaluation of the robustness of dual rail logic against DPA","authors":"A. Razafindraibe, P. Maurine, M. Robert","doi":"10.1109/ICICDT.2006.220792","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220792","url":null,"abstract":"Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA of dual rail logic is carried out. The result of this investigation is the formal identification of the design range in which dual rail logic can be considered as robust","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130051412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Fast and Accurate Monte Carlo Method for Interconnect Variation 一种快速准确的互连变化蒙特卡罗方法
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220828
M. Zhang, M. Olbrich, H. Kinzelbach, D. Seider, E. Barke
{"title":"A Fast and Accurate Monte Carlo Method for Interconnect Variation","authors":"M. Zhang, M. Olbrich, H. Kinzelbach, D. Seider, E. Barke","doi":"10.1109/ICICDT.2006.220828","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220828","url":null,"abstract":"For exploring the impact of manufacturing variation on interconnect characteristics, the basic Monte Carlo Method is accurate but computationally very expensive. To overcome the inherent speed limitation we developed an uncomplicated method employing the importance sampling technique. Using confidence intervals our results always take uncertainty into account. The application to a two dimensional interconnect model shows that our method is 23~93 times faster than the basic Monte Carlo method","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126928364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Dynamic Circuit Techniques in Deep Submicron Technologies: Domino Logic reconsidered 深亚微米技术中的动态电路技术:重新考虑Domino逻辑
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220790
C. Cornelius, S. Koppe, D. Timmermann
{"title":"Dynamic Circuit Techniques in Deep Submicron Technologies: Domino Logic reconsidered","authors":"C. Cornelius, S. Koppe, D. Timmermann","doi":"10.1109/ICICDT.2006.220790","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220790","url":null,"abstract":"Dynamic circuit techniques offer potential advantages over static CMOS. Domino circuits are the most widespread representative in high performance designs but suffer increasingly from deep submicron effects. This paper presents evaluations in terms of area, power dissipation, and propagation delay for static CMOS as well as for several Domino derivatives in a 90 nm technology. Finally, issues of reliability gained from practical experience for different testbenches are discussed","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133626193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Optimal Design of Monolithic Integrated DC-DC Converters 单片集成DC-DC转换器的优化设计
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220793
G. Schrom, P. Hazucha, F. Paillet, D. Gardner, S. T. Moon, T. Karnik
{"title":"Optimal Design of Monolithic Integrated DC-DC Converters","authors":"G. Schrom, P. Hazucha, F. Paillet, D. Gardner, S. T. Moon, T. Karnik","doi":"10.1109/ICICDT.2006.220793","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220793","url":null,"abstract":"Increasing supply current of high-performance microprocessors and limited real-estate available for power delivery in mobile platforms have spurred research of monolithic integrated DC-DC converters. Based on a model for the three key power loss mechanisms we derive an analytical solution for the optimal DC-DC converter design, linking power efficiency directly to CMOS front-end parameters and inductor technology. Further analysis shows that source-drain leakage, skin effect, eddy currents, and routing parasitics, although significant, don't change the optimal design","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121641251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
An Integrated Timing and Dynamic Supply Noise Verification Methodology for Nanometer CMOS SoC Designs 纳米CMOS SoC设计的集成时序和动态电源噪声验证方法
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220788
K. Shimazaki, M. Nagata, K. Sato
{"title":"An Integrated Timing and Dynamic Supply Noise Verification Methodology for Nanometer CMOS SoC Designs","authors":"K. Shimazaki, M. Nagata, K. Sato","doi":"10.1109/ICICDT.2006.220788","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220788","url":null,"abstract":"A semi-dynamic timing analysis flow of dynamic drop consideration applicable to a large-scale circuit is proposed. This technique is compared not only with SPICE simulation but with measurements using built-in noise probing and on-chip delay monitoring techniques, which validates the proposed flow","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124522127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simultaneous Peak and Average Power Optimization in Synchronous Sequential Designs Using Retiming and Multiple Supply Voltages 使用重定时和多个电源电压的同步顺序设计中同时峰值和平均功率优化
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220821
Atef Allam, J. Ramanujam
{"title":"Simultaneous Peak and Average Power Optimization in Synchronous Sequential Designs Using Retiming and Multiple Supply Voltages","authors":"Atef Allam, J. Ramanujam","doi":"10.1109/ICICDT.2006.220821","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220821","url":null,"abstract":"In this paper, we present a combination of basic retiming and multiple voltage scheduling (MVS) techniques in order to optimize dynamic peak power as well as average power consumption in synchronous sequential circuits under timing constraints. First, we devise a mixed-integer linear programming (MILP) formulation for the problem of scheduling for optimal peak and/or average power consumption through a unification of retiming and MVS techniques. Then, to alleviate the problem of variable explosion in MILP, we present a two-stage algorithm for peak and average power optimization. First, power-oriented retiming is proposed to restructure the input SDFG in order to achieve parallelization to favor nodes with high power consumption followed by an MILP formulation for peak and/or average power optimization using MVS technique","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124981691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-Gate MOSFETs with Back-Gate Control 具有后门控制的多栅极mosfet
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220797
T. Hiramoto, T. Nagumo
{"title":"Multi-Gate MOSFETs with Back-Gate Control","authors":"T. Hiramoto, T. Nagumo","doi":"10.1109/ICICDT.2006.220797","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220797","url":null,"abstract":"In this paper, we develop a design guideline for multi-gate MOSFET for Vth control. The design window of channel height (tSi) and width (wSi) to obtain both sufficiently large gamma and suppressed SCE in hp45 node LSTP devices is shown by 3D device simulation. The channel width dependence of gamma is also experimentally examined","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133555256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A Impact of Block Oxide on 50 nm Gate Length Planar MOSFETs 氧化块对50nm栅长平面mosfet的影响
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220812
Jyi-Tsong Lin, Y. Eng, Tai-Yi Lee, Kao-Cheng Lin, Kuo-Dong Huang
{"title":"A Impact of Block Oxide on 50 nm Gate Length Planar MOSFETs","authors":"Jyi-Tsong Lin, Y. Eng, Tai-Yi Lee, Kao-Cheng Lin, Kuo-Dong Huang","doi":"10.1109/ICICDT.2006.220812","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220812","url":null,"abstract":"In this paper, a new field-effect transistor (FET), silicon on partial insulator with block oxide (bSPI), is presented. To fabricate this novel device architecture, a sidewall spacer process is also exploited. For bSPIFET, this block oxide can block the most parts of the p-n junction between the substrate and the source/drain (S/D) region; thus, the junction leakage current is reduced dramatically. Likewise, thanks to the electric field between the body and the S/D region is isolated by the block oxide, the ultra-short-channel effects (USCEs) is also suppressed. In other words, the excellent device properties of the bSPIFET can be achieved, such as reduced drain-induced barrier lowering (DIBL), ultra low leakage (ULL), ideal subthreshold swing (SS), high drain output resistance and increase in the breakdown voltage. Moreover, owing to that the body of the bSPIFET device is bound to the substrate, both the floating-body effects (FBEs) and the self-heating effects (SHEs) are overcome simultaneously","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133840169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Application of Global Loops on ULSI Routing for DfY 全局环路在DfY的ULSI路由中的应用
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220822
P. Panitz, M. Olbrich, J. Koehl, E. Barke
{"title":"Application of Global Loops on ULSI Routing for DfY","authors":"P. Panitz, M. Olbrich, J. Koehl, E. Barke","doi":"10.1109/ICICDT.2006.220822","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220822","url":null,"abstract":"The number of circuit malfunctions due to opens increases with shrinking technologies. This requires reconsidering traditional tree based routing approaches for signal wiring. In this paper, we apply global loops to generate robust net topologies which are fully immune against single open faults. We show that the solution of the traveling salesperson problem yields a nearly optimal solution to the two edge connected subgraph problem. Additionally, we introduce a heuristic for finding additional segments which significantly reduce the delay. As result the critical area reduction is better than in previous published approaches which augment minimum Steiner trees","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123969952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Four-Trminal Double-ate Logic for LSTP Applications below 32-nm Technology Node 32nm以下LSTP应用的四端双通道逻辑
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220801
S. O'Uchi, Y. Liu, M. Masahara, T. Tsutsumi, K. Endo, T. Nakagawa, M. Hioki, T. Sekigawa, H. Koike, E. Suzuki
{"title":"Four-Trminal Double-ate Logic for LSTP Applications below 32-nm Technology Node","authors":"S. O'Uchi, Y. Liu, M. Masahara, T. Tsutsumi, K. Endo, T. Nakagawa, M. Hioki, T. Sekigawa, H. Koike, E. Suzuki","doi":"10.1109/ICICDT.2006.220801","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220801","url":null,"abstract":"A logic system consisting of four-terminal double-gate MOSFETs (4T-DGFETs) suppresses power consumption while it also improves processing efficiency by utilizing a flexible threshold-voltage control function by a second gate of 4T-DGFET. Based on the simulation calibrated with the fabricated device characteristics, it is shown that the 4T-DGFET logic is effective in low-standby-power applications below the half-pitch (hp) 32-nm technology node. A scaling strategy for the 4T-DG logic is also provided","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"3 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128651015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信