{"title":"Application of Global Loops on ULSI Routing for DfY","authors":"P. Panitz, M. Olbrich, J. Koehl, E. Barke","doi":"10.1109/ICICDT.2006.220822","DOIUrl":null,"url":null,"abstract":"The number of circuit malfunctions due to opens increases with shrinking technologies. This requires reconsidering traditional tree based routing approaches for signal wiring. In this paper, we apply global loops to generate robust net topologies which are fully immune against single open faults. We show that the solution of the traveling salesperson problem yields a nearly optimal solution to the two edge connected subgraph problem. Additionally, we introduce a heuristic for finding additional segments which significantly reduce the delay. As result the critical area reduction is better than in previous published approaches which augment minimum Steiner trees","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Conference on IC Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2006.220822","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The number of circuit malfunctions due to opens increases with shrinking technologies. This requires reconsidering traditional tree based routing approaches for signal wiring. In this paper, we apply global loops to generate robust net topologies which are fully immune against single open faults. We show that the solution of the traveling salesperson problem yields a nearly optimal solution to the two edge connected subgraph problem. Additionally, we introduce a heuristic for finding additional segments which significantly reduce the delay. As result the critical area reduction is better than in previous published approaches which augment minimum Steiner trees