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2006 IEEE International Conference on IC Design and Technology最新文献

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Single Event Leakage Current in Flash memory 闪存中的单事件泄漏电流
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220837
G. Cellere, L. Larcher, A. Paccagnella, A. Visconti, M. Bonanomi
{"title":"Single Event Leakage Current in Flash memory","authors":"G. Cellere, L. Larcher, A. Paccagnella, A. Visconti, M. Bonanomi","doi":"10.1109/ICICDT.2006.220837","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220837","url":null,"abstract":"Flash memories are the leader among nonvolatile memory technologies. Ionizing radiation impact their reliability both on the control circuitry and on the memory array itself. In particular, in FGs hit by ions the tracks of defects generated by ions in the tunnel oxide may result in a radiation induced leakage current (RILC), which can leads to retention problems in hit FGs. We are demonstrating and modeling this phenomenon in a state-of-the-art Floating Gate memory technology. We are also showing that RILC has a peculiar erratic behavior","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"16 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131091370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Totally Silicided (TOSI) Gates as an evolutionary metal gate solution for advanced CMOS technologies 全硅化(TOSI)栅极作为先进CMOS技术的一种进化的金属栅极解决方案
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220816
M. Muller, A. Mondot, D. Aimé, N. Gierczynski, G. Ribes, T. Skotnicki
{"title":"Totally Silicided (TOSI) Gates as an evolutionary metal gate solution for advanced CMOS technologies","authors":"M. Muller, A. Mondot, D. Aimé, N. Gierczynski, G. Ribes, T. Skotnicki","doi":"10.1109/ICICDT.2006.220816","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220816","url":null,"abstract":"In this paper, we show that totally silicided (TOSI) gate electrodes offer an interesting and industrially viable option for the integration of metal gate electrodes in advanced CMOS technologies as their integration requires only few modifications with respect to a CMOS standard flow. Moreover, the use of NiSi gives access to an electrode with a tunable mid-gap work function. The potential of TOSI-gate devices is demonstrated by integration and device results including fully operational SRAM cells and reliability data","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128261532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology Node for Embedded Applications 一种完全兼容嵌入式应用90纳米CMOS技术节点的浮体电池(FBC)
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220785
T. Hamamoto, Y. Minami, T. Shino, A. Sakamoto, T. Higashi, N. Kusunoki, K. Fujita, K. Hatsuda, T. Ohsawa, N. Aoki, H. Tanimoto, M. Morikado, H. Nakajima, K. Inoh, A. Nitayama
{"title":"A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology Node for Embedded Applications","authors":"T. Hamamoto, Y. Minami, T. Shino, A. Sakamoto, T. Higashi, N. Kusunoki, K. Fujita, K. Hatsuda, T. Ohsawa, N. Aoki, H. Tanimoto, M. Morikado, H. Nakajima, K. Inoh, A. Nitayama","doi":"10.1109/ICICDT.2006.220785","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220785","url":null,"abstract":"Floating body cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128Mb SOI DRAM with FBC has been designed and successfully developed. The memory cell design and the experimental results, such as the signal and the retention characteristics, are reviewed. The results of the fabricated SOI DRAM and the prospect as embedded memory are also discussed","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129526751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Low-Power Fully-Mosfet Voltage Reference Generator for 90 nm CMOS Technology 用于90nm CMOS技术的低功耗全mosfet电压基准发生器
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220834
G. D. Naro, G. Lombardo, C. Paolino, G. Lullo
{"title":"A Low-Power Fully-Mosfet Voltage Reference Generator for 90 nm CMOS Technology","authors":"G. D. Naro, G. Lombardo, C. Paolino, G. Lullo","doi":"10.1109/ICICDT.2006.220834","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220834","url":null,"abstract":"An integrated voltage reference generator, designed for being incorporated in standard 90-nm CMOS technology flash memories, is described in this paper. A fully MOSFET based approach, using also subthreshold operated devices, has been adopted in order to achieve low-voltage and low-power requirements and to overcome the difficulties of conventional band-gap reference circuits. The proposed circuit, based on current signals, internally generates two currents with opposite dependence on temperature. The two currents are added, thus canceling almost completely temperature dependence, and then linearly converted into the output voltage. For a temperature variation between -20degC and 90degC, the produced reference voltage shows a stability within 0.7%. The very low current consumption (1.3 muA), together with the possibility of operating at very low supply voltages (around 1V), make the circuit well suitable for applications in low-power low-voltage integrated circuits","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132505638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Mobility-Enhanced CMOS Technologies Using Strained Si/SiGe/Ge Channels 利用应变Si/SiGe/Ge通道的可迁移性增强CMOS技术
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220817
S. Takagi, T. Tezuka, T. Irisawa, S. Nakaharai, T. Numata, K. Usuda, T. Maeda, N. Sugiyama
{"title":"Mobility-Enhanced CMOS Technologies Using Strained Si/SiGe/Ge Channels","authors":"S. Takagi, T. Tezuka, T. Irisawa, S. Nakaharai, T. Numata, K. Usuda, T. Maeda, N. Sugiyama","doi":"10.1109/ICICDT.2006.220817","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220817","url":null,"abstract":"It has been well recognized that continuous increase in drive current is mandatory for successive growth of future CMOS LSIs. This means that the mobility enhancement has to keep being pursued in each technology node. For this purpose, a variety of local strain and global strain techniques have recently been developed and some of them have already been implemented in real products as presented in T. Ghani et al. (2003). This paper reports our recent approaches on the development of mobility-enhanced device structures based on the global strain substrates","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122648019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
New modules, materials and architectures for Flash Memory scaling 新的模块，材料和架构的闪存缩放
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220836
G. Molas, B. De Salvo
{"title":"New modules, materials and architectures for Flash Memory scaling","authors":"G. Molas, B. De Salvo","doi":"10.1109/ICICDT.2006.220836","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220836","url":null,"abstract":"In this paper, different solutions, fully compatible with current CMOS process, to extend the floating gate flash memory technology to the 45nm and possibly 32nm nodes, are presented. In particular, new modules (discrete traps memories, and more specifically silicon nanocrystal memories), new materials (high-k materials integrated in the tunnel barrier and/or interpoly layer) and innovative architectures (FinFlash memories) are discussed","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124704694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An active 90nm inductive signal noise testchip with realistic microprocessor signal buses 一种带有真实微处理器信号总线的90纳米有源感应信号噪声测试芯片
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220789
M. Elzinga, E. Chiprout, Chidi Dike, M. Wolfe, M. Kobrinsky
{"title":"An active 90nm inductive signal noise testchip with realistic microprocessor signal buses","authors":"M. Elzinga, E. Chiprout, Chidi Dike, M. Wolfe, M. Kobrinsky","doi":"10.1109/ICICDT.2006.220789","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220789","url":null,"abstract":"A 90nm inductance test chip that includes active drivers and on-die noise capture capabilities has been fabricated and measured in silicon. The purpose of the test chip was to quantify the inductive and capacitive noise effects on realistic microprocessor signal lines using typical inter-repeater lengths and signal-to-voltage-rail ratios. Measured results showed that signal inductive noise can potentially contend with capacitive noise and, in double-wide structures, can be of a greater effect than capacitive noise","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128913045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Physical Design Automation Challenges for 3D ICs 3D集成电路的物理设计自动化挑战
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220820
S. Sapatnekar
{"title":"Physical Design Automation Challenges for 3D ICs","authors":"S. Sapatnekar","doi":"10.1109/ICICDT.2006.220820","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220820","url":null,"abstract":"Recent advances in process technology have brought forth several options that have brought three-dimensional (3D) circuits within the realm of the possible and probable. This new design paradigm requires a major change in design methodologies, and an optimal 3D design looks very different from an optimal 2D design. Since the move from conventional 2D to 3D is inherently a topological change, it stands to reason that a number of 3D-specific problems lie in the domain of physical design. This paper addresses challenges related to physical design for 3D integrated circuits","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116726860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Nanoscale Si-based 3-dimensional MOSFETs 纳米尺度硅基三维mosfet
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220798
Donggun Park, Dong-Won Kim, B. Ryu
{"title":"Nanoscale Si-based 3-dimensional MOSFETs","authors":"Donggun Park, Dong-Won Kim, B. Ryu","doi":"10.1109/ICICDT.2006.220798","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220798","url":null,"abstract":"The authors introduce nanoscale CMOS transistors based on silicon technology to overcome the scaling limits such as area, physics, lithography, etc. For the scaling of planar transistors down to 50 nm, RCAT, PiFET, and twin SONOS memory cell transistors are developed. As the further scaling is required below 50 nm, 3 dimensional transistors such as FinFET, McFET, MBCFET, and TSNWFET are newly developed to overcome the physical scaling limits down to 10 nm with manufacturability and reliability","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126475019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
From oxide breakdown to device failure: an overview of post-breakdown phenomena in ultrathin gate oxides 从氧化物击穿到器件失效:超薄栅极氧化物击穿后现象概述
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220807
J. Suñé, E. Wu
{"title":"From oxide breakdown to device failure: an overview of post-breakdown phenomena in ultrathin gate oxides","authors":"J. Suñé, E. Wu","doi":"10.1109/ICICDT.2006.220807","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220807","url":null,"abstract":"In this paper, we present an overview of post-BD phenomena in ultra thin (1nm < TOX < 3 nm) oxides and couple this description to a discussion of the different methodologies proposed to deal with the post-BD reliability. We focus on the complete description of the statistics of the time to device failure (tFAIL) and of the residual time (tRES) from oxide BD to device failure, and on their scaling properties. Both intrinsic and extrinsic BD modes will be considered and the impact of burn-in will be briefly analyzed","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"14 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131388156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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