{"title":"3D集成电路的物理设计自动化挑战","authors":"S. Sapatnekar","doi":"10.1109/ICICDT.2006.220820","DOIUrl":null,"url":null,"abstract":"Recent advances in process technology have brought forth several options that have brought three-dimensional (3D) circuits within the realm of the possible and probable. This new design paradigm requires a major change in design methodologies, and an optimal 3D design looks very different from an optimal 2D design. Since the move from conventional 2D to 3D is inherently a topological change, it stands to reason that a number of 3D-specific problems lie in the domain of physical design. This paper addresses challenges related to physical design for 3D integrated circuits","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Physical Design Automation Challenges for 3D ICs\",\"authors\":\"S. Sapatnekar\",\"doi\":\"10.1109/ICICDT.2006.220820\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recent advances in process technology have brought forth several options that have brought three-dimensional (3D) circuits within the realm of the possible and probable. This new design paradigm requires a major change in design methodologies, and an optimal 3D design looks very different from an optimal 2D design. Since the move from conventional 2D to 3D is inherently a topological change, it stands to reason that a number of 3D-specific problems lie in the domain of physical design. This paper addresses challenges related to physical design for 3D integrated circuits\",\"PeriodicalId\":447050,\"journal\":{\"name\":\"2006 IEEE International Conference on IC Design and Technology\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-08-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Conference on IC Design and Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2006.220820\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Conference on IC Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2006.220820","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Recent advances in process technology have brought forth several options that have brought three-dimensional (3D) circuits within the realm of the possible and probable. This new design paradigm requires a major change in design methodologies, and an optimal 3D design looks very different from an optimal 2D design. Since the move from conventional 2D to 3D is inherently a topological change, it stands to reason that a number of 3D-specific problems lie in the domain of physical design. This paper addresses challenges related to physical design for 3D integrated circuits
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
