{"title":"纳米尺度硅基三维mosfet","authors":"Donggun Park, Dong-Won Kim, B. Ryu","doi":"10.1109/ICICDT.2006.220798","DOIUrl":null,"url":null,"abstract":"The authors introduce nanoscale CMOS transistors based on silicon technology to overcome the scaling limits such as area, physics, lithography, etc. For the scaling of planar transistors down to 50 nm, RCAT, PiFET, and twin SONOS memory cell transistors are developed. As the further scaling is required below 50 nm, 3 dimensional transistors such as FinFET, McFET, MBCFET, and TSNWFET are newly developed to overcome the physical scaling limits down to 10 nm with manufacturability and reliability","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Nanoscale Si-based 3-dimensional MOSFETs\",\"authors\":\"Donggun Park, Dong-Won Kim, B. Ryu\",\"doi\":\"10.1109/ICICDT.2006.220798\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors introduce nanoscale CMOS transistors based on silicon technology to overcome the scaling limits such as area, physics, lithography, etc. For the scaling of planar transistors down to 50 nm, RCAT, PiFET, and twin SONOS memory cell transistors are developed. As the further scaling is required below 50 nm, 3 dimensional transistors such as FinFET, McFET, MBCFET, and TSNWFET are newly developed to overcome the physical scaling limits down to 10 nm with manufacturability and reliability\",\"PeriodicalId\":447050,\"journal\":{\"name\":\"2006 IEEE International Conference on IC Design and Technology\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-08-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Conference on IC Design and Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2006.220798\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Conference on IC Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2006.220798","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The authors introduce nanoscale CMOS transistors based on silicon technology to overcome the scaling limits such as area, physics, lithography, etc. For the scaling of planar transistors down to 50 nm, RCAT, PiFET, and twin SONOS memory cell transistors are developed. As the further scaling is required below 50 nm, 3 dimensional transistors such as FinFET, McFET, MBCFET, and TSNWFET are newly developed to overcome the physical scaling limits down to 10 nm with manufacturability and reliability
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