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Discrete Dopant Fluctuation in Limited-Width FinFETs for VLSI Circuit Application: A Theoretical Study VLSI有限宽finfet中离散掺杂波动的理论研究
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220800
M. Chiang, Jeng-Nan Lin, Keunwoo Kim, C. Chuang
{"title":"Discrete Dopant Fluctuation in Limited-Width FinFETs for VLSI Circuit Application: A Theoretical Study","authors":"M. Chiang, Jeng-Nan Lin, Keunwoo Kim, C. Chuang","doi":"10.1109/ICICDT.2006.220800","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220800","url":null,"abstract":"The random dopant fluctuation (RDF) in double-gate (DG) devices is investigated via physical analyses and numerical simulations. Our results show that extremely scaled devices, especially FinFETs with narrow device width (fin height) in each individual fin, are susceptible to RDF effects. Even in an undoped silicon channel, the existence of unwanted impurity dopant will still have a significant impact on device characteristics. Design implication from RDF is also discussed","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116432878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ITFET: Inverted T Channel FET, A Novel Device architecture and circuits based on the ITFET ITFET:倒T沟道FET，一种基于ITFET的新型器件结构和电路
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220809
L. Mathew, M. Sadd, S. Kalpat, M. Zavala, T. Stephens, R. Mora, R. Rai, C. Parker, J. Vasek, D. Sing, R. Shinier, L. Prabhu, G. Workman, G. Ablen, Z. Shi, J. Saenz, B. Min, D. Burnett, B. Nguyen, J. Mogab, M. Chowdhury, W. Zhang, J. Fossum
{"title":"ITFET: Inverted T Channel FET, A Novel Device architecture and circuits based on the ITFET","authors":"L. Mathew, M. Sadd, S. Kalpat, M. Zavala, T. Stephens, R. Mora, R. Rai, C. Parker, J. Vasek, D. Sing, R. Shinier, L. Prabhu, G. Workman, G. Ablen, Z. Shi, J. Saenz, B. Min, D. Burnett, B. Nguyen, J. Mogab, M. Chowdhury, W. Zhang, J. Fossum","doi":"10.1109/ICICDT.2006.220809","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220809","url":null,"abstract":"The ITFET is novel device architecture; it offers significant advantages over planar and FinFET technologies. The ITFET uses traditional CMOS processing technologies and can be rapidly inserted into existing SOI process flows. Doped channel ITFET devices have been demonstrated future work will include undoped channel ITFET devices. Simulated performances of the ITFET devices predict these devices can meet the 45nm and 32nm device performance. This transistor architecture offers device, process and application advantages","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127505131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low Power and Flexible Braille Sheet Display with Organic FET's and Plastic Actuators 低功耗和柔性盲文片显示与有机场效应晶体管和塑料执行器
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220831
M. Takamiya, T. Sekitani, Y. Kato, S. Kawaguchi, T. Someya, T. Sakurai
{"title":"Low Power and Flexible Braille Sheet Display with Organic FET's and Plastic Actuators","authors":"M. Takamiya, T. Sekitani, Y. Kato, S. Kawaguchi, T. Someya, T. Sakurai","doi":"10.1109/ICICDT.2006.220831","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220831","url":null,"abstract":"Organic FETs (OFETs) are integrated with actuators, and a Braille sheet display is demonstrated. A newly developed back-gated OFETs SRAM and the circuits technology for the Braille sheet display to enhance speed, yield and lifetime are presented, which will be essential for future large-area electronics made with OFETs","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125895864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Timing Preservation in Wire Spreading Utilized for Yield Improvement 利用铺丝时定时保护提高成品率
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220830
T. Serdar, O. Omedes, B. Carpentier
{"title":"Timing Preservation in Wire Spreading Utilized for Yield Improvement","authors":"T. Serdar, O. Omedes, B. Carpentier","doi":"10.1109/ICICDT.2006.220830","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220830","url":null,"abstract":"Today's submicron technologies increase the IC sensitivity to the physical manufacturing defects, which results in poor initial product yield. It is well known that IC layout can be made more robust to the defects by making changes to the layout such as: adding extra vias in place of single vias (redundant via insertion), thickening thin wires (wire widening) and moving wires so that they are further apart (wire spreading). Today all these techniques are not timing aware and therefore can create additional timing violations. Wire spreading with no timing information in our experiments could create up to 490ps timing degradation. Even if the overall yield is improved, with such timing degradation, the design is not acceptable for manufacturing. This paper presents simple yet very effective timing preservation technique for wire spreading yield improvement at the post processing stage. Our results show that it is possible to control the timing during wire spreading - setup/hold slack stays the same or improved comparing to the initial slack","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130800565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design-Technology Interface: What will replace design rules for DDSM? 设计-技术接口:什么将取代DDSM的设计规则?
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220819
M. Lavin
{"title":"Design-Technology Interface: What will replace design rules for DDSM?","authors":"M. Lavin","doi":"10.1109/ICICDT.2006.220819","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220819","url":null,"abstract":"Summary form only given. It is now well-accepted that CMOS technology has entered a new era where the rapid, steady quantitative scaling of performance, density, etc. appears to be slowing, and is subject to new impediments (noise, static and dynamic power) as well as qualitative, sometimes disruptive change in processes, materials, and devices. One of the main contributors to this slowing and complication is the increasing impact of variability. What I want to discuss in this paper is how variability also impacts the interface between chip design and technology development. Historically, this interface was represented by design rules and device/wire models that scaled smoothly over time; this was reflected by the fact that IBM's processor technologies from the frac12 micron node down to the 130nm node used a (mostly) stable set of scalable design rules and circuit models in which there was a single \"NRN\" dimension of variability. Going forward, it is clear that the models and the design tools that use them have to capture a more complete understanding of systematic and random variability, and conventional design rules have to replaced by other means for representing to designers what the new technologies are (and are not) capable of. I spent most of my talk describing some potential replacements for conventional design rules","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127734579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of CMOS Technology Scaling on SRAM Standby Leakage Reduction techniques CMOS技术缩放对SRAM待机减漏技术的影响
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220778
O. Thomas, M. Belleville, F. Jacquet, P. Flatresse
{"title":"Impact of CMOS Technology Scaling on SRAM Standby Leakage Reduction techniques","authors":"O. Thomas, M. Belleville, F. Jacquet, P. Flatresse","doi":"10.1109/ICICDT.2006.220778","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220778","url":null,"abstract":"This paper investigates leakage reduction techniques for a conventional 6T SRAM cell in advanced technologies. The most promising leakage reduction techniques that have been proposed are presented and compared for the 130-nm and 65-nm technology nodes. More specifically, the impact of the evolution of the gate tunneling and substrate currents is studied considering the efficiency of those techniques. Finally, the best techniques for leakage reduction in sub 100-nm SRAM cell, and guidelines on how to merge them in order to reach an optimum, are proposed","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133787720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Robust 45nm porous low-k process integration with well-controlled plasma process damage and moisture uptake 坚固的45纳米多孔低k工艺集成与良好控制等离子体过程损伤和水分吸收
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220804
N. Matsunaga
{"title":"Robust 45nm porous low-k process integration with well-controlled plasma process damage and moisture uptake","authors":"N. Matsunaga","doi":"10.1109/ICICDT.2006.220804","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220804","url":null,"abstract":"In this paper, robust 45nm porous low-k process integration with well-controlled plasma process damage and moisture uptake will be discussed","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114033052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Self-Tuning Dynamic Voltage Scaled Processor Using Delay-Error Detection and Correction 一种基于延迟误差检测与校正的自调谐动态电压缩放处理器
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220829
Shidhartha Das, D. Roberts, Seokwoo Lee, Sanjay Pant, D. Blaauw, T. Austin, T. Mudge, K. Flautner
{"title":"A Self-Tuning Dynamic Voltage Scaled Processor Using Delay-Error Detection and Correction","authors":"Shidhartha Das, D. Roberts, Seokwoo Lee, Sanjay Pant, D. Blaauw, T. Austin, T. Mudge, K. Flautner","doi":"10.1109/ICICDT.2006.220829","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220829","url":null,"abstract":"In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18mum technology. The processor employs a delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point. It achieves 44% energy savings over the worst case operating conditions for a 0.1% targeted error rate at a fixed frequency of 120MHz","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"371 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123267096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Suitability of FinFET technology for low-power mixed-signal applications FinFET技术在低功率混合信号应用中的适用性
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220796
B. Parvais, C. Gustin, V. De Heyn, J. Loo, M. Dehan, V. Subramanian, A. Mercha, N. Collaert, R. Rooyackers, M. Jurczak, P. Wambacq, S. Decoutere
{"title":"Suitability of FinFET technology for low-power mixed-signal applications","authors":"B. Parvais, C. Gustin, V. De Heyn, J. Loo, M. Dehan, V. Subramanian, A. Mercha, N. Collaert, R. Rooyackers, M. Jurczak, P. Wambacq, S. Decoutere","doi":"10.1109/ICICDT.2006.220796","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220796","url":null,"abstract":"Wireless applications require a low power technology that enables digital/analog/RF functions on the same chip. FinFET technology presents a competitive alternative to planar CMOS as it features good digital, analog and low-frequency noise performances. Also, very good matching performance is presented here for the first time. Moreover, FinFETs are shown to be attractive for low-power applications below 10 GHz. The suitability of Fin varactors is evaluated and tradeoffs are given. An inductorless oscillator with large tuning range (1-8.5 GHz) for low-power wideband applications is demonstrated for the first time","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128386822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A Low-Voltage Process Corner Insensitive Subthreshold CMOS Voltage Reference Circuit 一种低压过程角不敏感亚阈值CMOS电压参考电路
2006 IEEE International Conference on IC Design and Technology Pub Date : 2006-08-14 DOI: 10.1109/ICICDT.2006.220833
Hongchin Lin, Dern-Koan Chang
{"title":"A Low-Voltage Process Corner Insensitive Subthreshold CMOS Voltage Reference Circuit","authors":"Hongchin Lin, Dern-Koan Chang","doi":"10.1109/ICICDT.2006.220833","DOIUrl":"https://doi.org/10.1109/ICICDT.2006.220833","url":null,"abstract":"A reference voltage circuit is presented for generating a constant reference voltage of 278mV using subthreshold characteristics of 0.18mum CMOS technology at supply voltages from 0.8V to 2.6V with total current of 3.6muA. The threshold voltage variation due to process corner variation is minimized by a threshold voltage tracking technique between the normal and high threshold NMOS transistors. In the mean time, channel-length modulation effect is also compensated. The proposed circuit on chip area of 0.04mm2 achieves the total reference voltage variation of 2.5mV for various process corners and temperature variation from -20degC to 120degC","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130730201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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