L. Mathew, M. Sadd, S. Kalpat, M. Zavala, T. Stephens, R. Mora, R. Rai, C. Parker, J. Vasek, D. Sing, R. Shinier, L. Prabhu, G. Workman, G. Ablen, Z. Shi, J. Saenz, B. Min, D. Burnett, B. Nguyen, J. Mogab, M. Chowdhury, W. Zhang, J. Fossum
{"title":"ITFET: Inverted T Channel FET, A Novel Device architecture and circuits based on the ITFET","authors":"L. Mathew, M. Sadd, S. Kalpat, M. Zavala, T. Stephens, R. Mora, R. Rai, C. Parker, J. Vasek, D. Sing, R. Shinier, L. Prabhu, G. Workman, G. Ablen, Z. Shi, J. Saenz, B. Min, D. Burnett, B. Nguyen, J. Mogab, M. Chowdhury, W. Zhang, J. Fossum","doi":"10.1109/ICICDT.2006.220809","DOIUrl":null,"url":null,"abstract":"The ITFET is novel device architecture; it offers significant advantages over planar and FinFET technologies. The ITFET uses traditional CMOS processing technologies and can be rapidly inserted into existing SOI process flows. Doped channel ITFET devices have been demonstrated future work will include undoped channel ITFET devices. Simulated performances of the ITFET devices predict these devices can meet the 45nm and 32nm device performance. This transistor architecture offers device, process and application advantages","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Conference on IC Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2006.220809","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The ITFET is novel device architecture; it offers significant advantages over planar and FinFET technologies. The ITFET uses traditional CMOS processing technologies and can be rapidly inserted into existing SOI process flows. Doped channel ITFET devices have been demonstrated future work will include undoped channel ITFET devices. Simulated performances of the ITFET devices predict these devices can meet the 45nm and 32nm device performance. This transistor architecture offers device, process and application advantages
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