Timing Preservation in Wire Spreading Utilized for Yield Improvement

Abstract

Today's submicron technologies increase the IC sensitivity to the physical manufacturing defects, which results in poor initial product yield. It is well known that IC layout can be made more robust to the defects by making changes to the layout such as: adding extra vias in place of single vias (redundant via insertion), thickening thin wires (wire widening) and moving wires so that they are further apart (wire spreading). Today all these techniques are not timing aware and therefore can create additional timing violations. Wire spreading with no timing information in our experiments could create up to 490ps timing degradation. Even if the overall yield is improved, with such timing degradation, the design is not acceptable for manufacturing. This paper presents simple yet very effective timing preservation technique for wire spreading yield improvement at the post processing stage. Our results show that it is possible to control the timing during wire spreading - setup/hold slack stays the same or improved comparing to the initial slack