{"title":"New modules, materials and architectures for Flash Memory scaling","authors":"G. Molas, B. De Salvo","doi":"10.1109/ICICDT.2006.220836","DOIUrl":null,"url":null,"abstract":"In this paper, different solutions, fully compatible with current CMOS process, to extend the floating gate flash memory technology to the 45nm and possibly 32nm nodes, are presented. In particular, new modules (discrete traps memories, and more specifically silicon nanocrystal memories), new materials (high-k materials integrated in the tunnel barrier and/or interpoly layer) and innovative architectures (FinFlash memories) are discussed","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Conference on IC Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2006.220836","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, different solutions, fully compatible with current CMOS process, to extend the floating gate flash memory technology to the 45nm and possibly 32nm nodes, are presented. In particular, new modules (discrete traps memories, and more specifically silicon nanocrystal memories), new materials (high-k materials integrated in the tunnel barrier and/or interpoly layer) and innovative architectures (FinFlash memories) are discussed