Four-Trminal Double-ate Logic for LSTP Applications below 32-nm Technology Node

Abstract

A logic system consisting of four-terminal double-gate MOSFETs (4T-DGFETs) suppresses power consumption while it also improves processing efficiency by utilizing a flexible threshold-voltage control function by a second gate of 4T-DGFET. Based on the simulation calibrated with the fabricated device characteristics, it is shown that the 4T-DGFET logic is effective in low-standby-power applications below the half-pitch (hp) 32-nm technology node. A scaling strategy for the 4T-DG logic is also provided