S. O'Uchi, Y. Liu, M. Masahara, T. Tsutsumi, K. Endo, T. Nakagawa, M. Hioki, T. Sekigawa, H. Koike, E. Suzuki
{"title":"32nm以下LSTP应用的四端双通道逻辑","authors":"S. O'Uchi, Y. Liu, M. Masahara, T. Tsutsumi, K. Endo, T. Nakagawa, M. Hioki, T. Sekigawa, H. Koike, E. Suzuki","doi":"10.1109/ICICDT.2006.220801","DOIUrl":null,"url":null,"abstract":"A logic system consisting of four-terminal double-gate MOSFETs (4T-DGFETs) suppresses power consumption while it also improves processing efficiency by utilizing a flexible threshold-voltage control function by a second gate of 4T-DGFET. Based on the simulation calibrated with the fabricated device characteristics, it is shown that the 4T-DGFET logic is effective in low-standby-power applications below the half-pitch (hp) 32-nm technology node. A scaling strategy for the 4T-DG logic is also provided","PeriodicalId":447050,"journal":{"name":"2006 IEEE International Conference on IC Design and Technology","volume":"3 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Four-Trminal Double-ate Logic for LSTP Applications below 32-nm Technology Node\",\"authors\":\"S. O'Uchi, Y. Liu, M. Masahara, T. Tsutsumi, K. Endo, T. Nakagawa, M. Hioki, T. Sekigawa, H. Koike, E. Suzuki\",\"doi\":\"10.1109/ICICDT.2006.220801\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A logic system consisting of four-terminal double-gate MOSFETs (4T-DGFETs) suppresses power consumption while it also improves processing efficiency by utilizing a flexible threshold-voltage control function by a second gate of 4T-DGFET. Based on the simulation calibrated with the fabricated device characteristics, it is shown that the 4T-DGFET logic is effective in low-standby-power applications below the half-pitch (hp) 32-nm technology node. A scaling strategy for the 4T-DG logic is also provided\",\"PeriodicalId\":447050,\"journal\":{\"name\":\"2006 IEEE International Conference on IC Design and Technology\",\"volume\":\"3 4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-08-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Conference on IC Design and Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2006.220801\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Conference on IC Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2006.220801","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Four-Trminal Double-ate Logic for LSTP Applications below 32-nm Technology Node
A logic system consisting of four-terminal double-gate MOSFETs (4T-DGFETs) suppresses power consumption while it also improves processing efficiency by utilizing a flexible threshold-voltage control function by a second gate of 4T-DGFET. Based on the simulation calibrated with the fabricated device characteristics, it is shown that the 4T-DGFET logic is effective in low-standby-power applications below the half-pitch (hp) 32-nm technology node. A scaling strategy for the 4T-DG logic is also provided
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