Delay and Power Monitoring Scheme for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control

Abstract

This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage VDD and threshold voltage VTH in active and standby modes. On the basis of delay monitoring results, either VDD control or VTH control is selected, in order to avoid any oscillation problem between them in the active mode. With respect to power monitoring, experimental results with a 90-nm CMOS device show that it reduces power consumption by making it possible (1) to maintain a certain switching current ISW / leakage current ILEAK ratio in the active mode, and (2) to detect optimum body bias conditions (subthreshold current ISUBTH = substrate current ISUB) within an error of less than 20 % with respect to actual minimum leakage current values in the standby mode