A scalable Stacked Gate NOR/NAND Flash Technology compatible with high-k and metal gates for sub 45nm generations

Abstract

In this paper a scalable stacked gate technology with self-aligned floating gate (FG) is presented. It can be used for both NOR and NAND flash architectures. By introducing high-k materials for the interpoly dielectric (IPD) a planar structure can be used, which allows a much denser structure. It is also shown that the planar structure of the memory cell facilitates the introduction of metal gates. The successful integration of a 110nm stacked gate transistor with high-k IPD and TiN metal gate is illustrated