Impact of Advanced SOI Substrates on Device Architecture and Design

Abstract

The engineering of SOI substrates has allowed for optimization of MOSFET performance while minimizing leakage and parasitic elements. Design innovations have amplified the SOI benefits with a significant reduction of the cost of ownership. To move beyond the 90nm IC node, mobility enhancing strain techniques have been added to the CMOS process. While strained silicon on insulator appears to be a solution for reducing power consumption without affecting the device performance, SOI on high resistivity substrates offers a solution tailored to RF applications. An overview of the advances in Smart Cuttrade engineered substrates will be given, and their impact on device design will be discussed