Reviews and Prospects of Nanoscale SRAMs

Abstract

Designing 6-T SRAM cells is becoming more difficult as devices are scaled down and VDD is reduced. This paper describes soft error, the standby current, and the static noise margin for the low-voltage designs that must be carefully considered. First, cosmic-ray-induced multicell errors, which have now become a serious problem, are investigated. A new circuit architecture is proposed for the handling of cosmic-ray-induced multicell errors. Next, recent developments to suppress tunnel leakage currents for low-retention-current SRAMs are presented. Finally, future prospects of SRAM cells are discussed in terms of low-voltage designs. We propose a new SRAM cell using a new MOSFET on an ultra-thin BOX