27th European Solid-State Device Research Conference最新文献

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Theory and modelling of organic field effect transistors 有机场效应晶体管的理论与建模
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194509
Gernot Paasch, S. Scheinert, R. Tecklenburg
{"title":"Theory and modelling of organic field effect transistors","authors":"Gernot Paasch, S. Scheinert, R. Tecklenburg","doi":"10.1109/ESSDERC.1997.194509","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194509","url":null,"abstract":"In organic FET ́s (OFET) the active layer is an organic material. Until now measured current characteristics have been analyzed by using the most simple equation for the current. But the design of the OFET is not common in electronics. As demonstrated by our 2D simulations of analogous silicon devices this design leads to several peculiarities. We developed analytical models which incorporate these peculiarities and reproduce the simulated current characteristics with less than 3 to 5% error. As first applications we fitted published current characteristics of OFET ́s and determined in this way material parameters. Zero field mobility μ0 is low and indicate hopping transport. Large flat band voltages must origin from oxide/interface charges. Satisfactory fits are possible only by assuming velocity saturation unknown till now for hopping systems. The ratio vs/μ0 ~ 1.5⋅104V/cm can be explained theoretically.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123694395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Selectively-Implanted Collector Profile Optimisation for High-Speed Vertical Bipolar Transistors 高速垂直双极晶体管的选择性植入集电极结构优化
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194427
M. S. Peter, G. Hurkx, C. E. Timmering
{"title":"Selectively-Implanted Collector Profile Optimisation for High-Speed Vertical Bipolar Transistors","authors":"M. S. Peter, G. Hurkx, C. E. Timmering","doi":"10.1109/ESSDERC.1997.194427","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194427","url":null,"abstract":"The in uence of a selectively-implanted collector on the performance of a high-speed vertical bipolar transistor has been studied using Design of Experiments methods. Depending on the epilayer thickness two different types of behaviour are found for fT,max and BVCE0.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130554639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Surface recombination velocity measurement in SPEG SOS MOSFETs by bipolar gain characterisation 用双极增益特性测量SPEG SOS mosfet的表面复合速度
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194489
P.B. Stevens, C. Patel, J. Kerr, C. Shaw
{"title":"Surface recombination velocity measurement in SPEG SOS MOSFETs by bipolar gain characterisation","authors":"P.B. Stevens, C. Patel, J. Kerr, C. Shaw","doi":"10.1109/ESSDERC.1997.194489","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194489","url":null,"abstract":"Parasitic lateral bipolar gain characterisations were perfonned on silicon­ on-insulator (SOl) nMOSFETs with body contacts. The material was .. solid phase epitaxial growth (SPEG) silicon-on-sapphire (SOS). The behaviour of the gain was found to be dominated by surface recombina­ tion with a surface recombination velocity of 3xlO\" cm S-I, in agreement with three-level charge pumping measurements. A simple DC electrical characterisation technique is proposed for measuring the surface recombination velocity associated with interface states in MOSFETs where the gate-controlled bipolar gain is dominated by surface .recombi­ nation.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132378135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Examination of theTransient Drift-Diffusion and Hydrodynamic Modeling Accuracy for SiGe HBTs by 2D Monte-Carlo Device Simulation 基于二维蒙特卡罗器件仿真的SiGe HBTs瞬态漂移扩散和流体动力学建模精度检验
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194397
B. Neinhus, P. Graf, S. Decker, B. Meinerzhagen
{"title":"Examination of theTransient Drift-Diffusion and Hydrodynamic Modeling Accuracy for SiGe HBTs by 2D Monte-Carlo Device Simulation","authors":"B. Neinhus, P. Graf, S. Decker, B. Meinerzhagen","doi":"10.1109/ESSDERC.1997.194397","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194397","url":null,"abstract":"The critical device dimensions in advanced SiGe HBTs are extremely small ( 20nm). As a consequence the validity of conventional numerical device models becomes questionable. Therefore the transient modeling accuracy of Drift-Diffusion and Hydrodynamic transport modeling is examined in this paper for an advanced SiGe HBT by means of a Monte-Carlo reference device model. The result shows that the Hydrodynamic Model should be prefered for the engineering design of advanced SiGe HBTs.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126559651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Patterning of Pt/RuO2 electrodes for Pb(Zr,Ti)O3 in an Inductively Coupled Cl2/O2 Plasma 电感耦合Cl2/O2等离子体中Pb(Zr,Ti)O3的Pt/RuO2电极的图形化
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194537
S. Park, J. Lee, H. Jung, M. Jeon, D. Choi
{"title":"Patterning of Pt/RuO2 electrodes for Pb(Zr,Ti)O3 in an Inductively Coupled Cl2/O2 Plasma","authors":"S. Park, J. Lee, H. Jung, M. Jeon, D. Choi","doi":"10.1109/ESSDERC.1997.194537","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194537","url":null,"abstract":"Inductively coupled plasma excited by a helical antenna is used to pattern Pt/RuOz electrodes for PZT. The hybrid electrode of thin Pt on thicker RuOz layer has been studied because of good leakage current characteristics of Pt and easy etch characteristics of RuOz. The etch rates and selectivities to oxide hard mask have been measured for each of Pt and RuOz in terms of <nICh mixture ratio. The ratio of 10% Cl and 90%· Oz has been chosen for the optimum condition, and patterning of sub-half micron electrodes is demonstrated.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122245307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Full Band Monte-Carlo Device Simulation of an 0.1 um N-Channel MOSFET in Strained Silicon Material 应变硅材料中0.1 um n沟道MOSFET全频带蒙特卡罗器件模拟
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194400
S. Keith, F. M. Bufler, B. Meinerzhagen
{"title":"Full Band Monte-Carlo Device Simulation of an 0.1 um N-Channel MOSFET in Strained Silicon Material","authors":"S. Keith, F. M. Bufler, B. Meinerzhagen","doi":"10.1109/ESSDERC.1997.194400","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194400","url":null,"abstract":"Full band Monte Carlo device simulation is applied in this paper for a projection of the performance advantages of NMOS transistors with surface channels in strained Si in comparison to conventional Si NMOSTs. For strained Si grown on a Si0 7Ge0 3 buffer an advantage of 30 % in terms of maximum Ion is found.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121088695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
New parameter extraction method for the simulation of the space charge created by Fowler-Nordheim electron injections in the gate oxide of MOS devices 采用新的参数提取方法模拟MOS器件栅极氧化物中Fowler-Nordheim电子注入产生的空间电荷
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194510
G. Auriel, J. Dubuc, B. Sagnes, J. Oualid, G. Ghibaudo, P. Boivin
{"title":"New parameter extraction method for the simulation of the space charge created by Fowler-Nordheim electron injections in the gate oxide of MOS devices","authors":"G. Auriel, J. Dubuc, B. Sagnes, J. Oualid, G. Ghibaudo, P. Boivin","doi":"10.1109/ESSDERC.1997.194510","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194510","url":null,"abstract":"A new procedure to analyze the oxide space charge created during a Fowler-Nordheim electron injection in metal-oxidesemiconductor devices is presented. This procedure was used to study the evolution of the centroid and the areal density relative to each component of the space charge with the electric field applied during the injection. The occupation probabilities of donor and acceptor like traps created in the oxide during stress are also determined.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116091821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cost effective simulation of three-dimensional effects in the shallow trench isolation process 成本效益的模拟在浅沟隔离过程中的三维效应
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194467
P. Sallagoity, M. Ada‐Hanifi, A. Poncet
{"title":"Cost effective simulation of three-dimensional effects in the shallow trench isolation process","authors":"P. Sallagoity, M. Ada‐Hanifi, A. Poncet","doi":"10.1109/ESSDERC.1997.194467","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194467","url":null,"abstract":"As dimensions decrease, the device performances of MOS transistors are considerably more dependent on narrow channel effects. These effects are mainly due to lateral isolation, and can be better understood by means of three-dimensional simulation. In this paper, a simple method to investigate 3D effects induced by shallow trench isolation (STI) is presented; the approach which is based on suitable combinations of 2D simulations in planar cross sections is very cost effective in comparison with coupled process and device simulations in three dimensions. This method has been validated with respect to 3D device simulations, and has been applied to the analysis of the impact of certain process parameters on device performances which could not be achieved with present commercial 3D simulators.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"617 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116202727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Electro-Thermal Interaction on Circuit Level under the Influence of Packaging 封装影响下电路层面的电热相互作用
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194465
G. Digele, S. Lindenkreuz, E. Kasper
{"title":"Electro-Thermal Interaction on Circuit Level under the Influence of Packaging","authors":"G. Digele, S. Lindenkreuz, E. Kasper","doi":"10.1109/ESSDERC.1997.194465","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194465","url":null,"abstract":"Selfheating and electro-thermal interaction is a serious problem in the eld of analog controlled power applications. Power generating elements and temperature critical components propagate heat and sense the instantaneous temperature during an electrothermal circuit simulation. The thermal conductivity of silicon is temperature dependent. We present fully coupled electro-thermal simulation by solving the nonlinear heat di usion equation in silicon while taking into account the in uence of packaging.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121184211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Junctions design guidelines for 0.18um CMOS 0.18um CMOS结设计指南
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194447
R. Gwoziecki, T. Skotnicki, P. Bouillon, A. Poncet
{"title":"Junctions design guidelines for 0.18um CMOS","authors":"R. Gwoziecki, T. Skotnicki, P. Bouillon, A. Poncet","doi":"10.1109/ESSDERC.1997.194447","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194447","url":null,"abstract":"In this paper, we report on the influence of junction depth Xj on Ion/Ioff tradeoff. It is shown that short channel effect is almost independent of Xj on condition that Xj does not impact on ∆ L. We demonstrate that it is only via this latter dependence between Xj and ∆ L, that the Vth-vs-Xj implicit dependence comes to play. In addition, our simulation results show that Ion increases significantly with deepening junction (at constant Leff) without degrading Ioff. With this new understanding, junction design guidelines for 0.18um CMOS can be revised. Introduction We present the impact of the junction depth Xj on NMOS performances, by studying a variety of implanted MDD architectures. In order to control the Short Channel Effect (SCE) and the Drain Induced Barrier Lowering (DIBL), it is commonly accepted that Xj should be drastically diminished. On the other hand shallow junctions lead to an increase in parasitic resistance and involve increased process complexity [1-2]. In this paper, it is shown that, thanks to the use of retrograde channel profiles (RCP), only the lateral penetration of the junctions (∆L) is still a critical parameter, whereas the sensitivity to junction depth itself vanishes. Process key-steps The RCP architecture was achieved thanks to Indium implantation. A 40Å gate oxide was grown in 750°C wet ambient. The gates were patterned using the Phase Shift Mask I-Line Lithography, in order to obtain gate lengths down to 0.15μm. Several implantation conditions were tested for the extensions (Tab. 1). The source/drain N+ regions were implanted with Arsenic 2.1015at/cm-2 60keV after 0.1μm spacer formation. The activation was insured by an RTA at 950°C 30\", followed by common back-end process. NMOS devices have been characterized by extracting junction dependent parameters, such as parasitic resistance Rs and ∆L. The \"Shift and Ratio\" method was used [3-4], in order to overcome the limitations of \"L array\" methods. Analysis of conventional approach 0.18 m gate length NMOS transistors have been fabricated using RCP architecture (Indium 1.1e13cm-2 160keV) and MDD extensions (Arsenic 2e14cm-2 40keV). Despite the strongly doped extensions, these devices do not exhibit punchthrough (Fig. 1), the subthreshold slope is very good (80mV/dec @ Vd=1.8V), and the DIBL is well controlled (80mV). Nevertheless, a low threshold voltage leads to a high Ioff current (13nA/μm), with a Ion current of 530μA/μm, see Fig. 2. Moreover, any reduction in junction depth and/or increase in channel doping level would certainly worsen the Ion current even further, because of the increase in series resistances and/or body effect, respectively. In order to improve this trade-off and establish useful guidelines for junction design, we first analyzed the influence of junction depth Xj on the SCE. When plotted as a function of gate length (Fig. 3), the roll-off (defined as Vth[Lg]-Vth[Lg=5μm]) is increased with increasing junction depth. In contrast, when plotted as a f","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122783229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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