27th European Solid-State Device Research Conference最新文献_第4页

Two-dimensional analytical model of subthreshold current in fully-depleted SOI MOSFETs 全耗尽SOI mosfet亚阈值电流的二维解析模型

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194519

S. Pidin, H. Kurino, M. Koyanagi

引用次数: 1

The Design and Characterisation of a SiGe I2L Technology 一种sigi2l技术的设计与表征

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194437

N. E. Moiseiwitsch, G. P. Kennedy, S. Wainwright, P. Ashburn, S. Hall

引用次数: 0

An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface 臭氧化多晶硅/单晶硅界面多晶硅发射极双极晶体管的研究

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194454

S. Niel, C. Hernandez, R. Pantel, I. Sagnes, M. Berenguer, J. Kirtsch, A. Monroy, A. Chantre, G. Vincent

{"title":"An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface","authors":"S. Niel, C. Hernandez, R. Pantel, I. Sagnes, M. Berenguer, J. Kirtsch, A. Monroy, A. Chantre, G. Vincent","doi":"10.1109/ESSDERC.1997.194454","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194454","url":null,"abstract":"This paper reports the development of a new polysilicon/monosilicon interface preparation technique to adjust bipolar transistor properties. The interest of this new technique is demonstrated using physical characterizations, static and dynamic measurements on a 200mm 0.5μm BiCMOS technology. I) Introduction Oxygen at the poly/mono interface significantly affects the performances of poly emitter bipolar transistors. In particular, it is well known that an interfacial oxide layer increases the current gain and emitter resistance [1]. The aim of this paper is to evaluate new techniques for interfacial oxide formation. For the first time, a thin oxide layer has been introduced at the interface between in-situ doped emitter poly and Si using two different types of ozonization processes. We discuss the experimental results obtained on devices fabricated in a 200mm 0.5μm quasi self-aligned BiCMOS technology [2], and integrating an ozonized poly/mono interface. II) Interface preparation The use of ozone (O3) is advantageous for the combustion of possible hydrocarbon residues on the silicon surface and for its passivation and stabilization in time. In order to test different interfacial oxide thicknesses, two different ozone processes have been developed: i ) The first, HF + dry O3, corresponds to an O3 gaseous treatment after the well-known wet HF last clean. The interfacial oxide was obtained in the vapor phase cleaning module of an AST machine at room temperature under 100 hPa for 60sec, and its thickness is around 0.5-0.7nm as deduced from ellipsometric measurements [3]. i i ) The second, HF + wet O3, corresponds to a wet cleaning after the classical HF last, the O3 gas being diluted in water inside the CHAMBER FLOW machine before the deposition process. The equivalent oxide thickness (measured with a fixed refraction index of 1.465) of the interfacial layer is twice that of in the previous case (1nm). Diiodomethane contact angle measurements, which are sensitive to surface properties [4], suggest that in both cases, there is oxide growth (by analogy with reference thermal oxide) (Fig.1). As shown in Fig.1, the stability of the HF+dry O3 interface is similar to that of thermal oxide, while the HF+wet O3 changes more rapidly, as does the more conventional RCA prepared interface (Fig.2). The HF+dry O3 process thus appears to be a good choice for stable thin poly/mono interfacial oxide preparation, allowing a longer delay time before polysilicon emitter deposition. Fig.1: Diiodomethane contact angle evolution in time for thermal oxide,HF+dryO3, HF+wetO3 Fig.2: Diiodomethane contact angle evolution in time for RCA, HF+dryO3, HF+wetO3 III) Experimental results In our 0.5μm BiCMOS technology the emitter window is opened by dry etching in an oxide layer (800A thickness) (superposition of deposited oxide and thermal oxide). Immediately after the interface preparation (discussed above), the wafers were loaded in the in-situ doped polysilicon reactor. The tota","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133913096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An alternative method to monitor and control the IC temperature in the 4.2-77 K range 在4.2-77 K范围内监测和控制IC温度的另一种方法

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194459

E. Gutiérrez-D., J. De la Hidalga-W, M. Deen, S. Koshevaya

引用次数: 2

The Planar-Doped-Barrier-FET: MOSFET Overcomes Conventional Limitations 平面掺杂势垒场效应管:MOSFET克服了传统的限制

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194506

W. Hansch, V. Rao, I. Eisele

引用次数: 3

An Improved Technology for Elevated Source/Drain MOSFETS 一种改进的高架源/漏极mosfet技术

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194414

A. Waite, D. Howard, S. Kubicek, M. Caymax, K. De Meyer, A. Evans

引用次数: 0

Efficient Parameter Extraction and Statistical Analysis for a 0.25um low-power CMOS Process 0.25um低功耗CMOS工艺的高效参数提取与统计分析

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194514

E.V. Saavedra Diaz, K. McCarthy, D. Klaassen, A. Mathewson

引用次数: 3

Dynamic floating body effects in PD SOI MOSFETs biased in the kink region 偏置在扭结区的PD SOI mosfet的动态浮体效应

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194481

L. Perron, C. Hamaguchi, A. Lacaita, M. Maegewa, Y. Yamaguchi

引用次数: 1

A 9 GHz Bandwith Preamplifier in 10 Gbps Optical Receiver Using SiGe Base HBT 基于SiGe基带HBT的10gbps光接收机9ghz前置放大器

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194439

B. Ryum, D. Cho, S.-M. Lee, T. Han

引用次数: 3

A Study of Temperature Distribution in SOI-Smart Power Devices in Transient Conditions by Optical Interferometry 光干涉法研究soi智能功率器件瞬态温度分布

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194478

N. Seliger, D. Pogany, C. Furbock, P. Habaš, E. Gornik, M. Stoisiek

{"title":"A Study of Temperature Distribution in SOI-Smart Power Devices in Transient Conditions by Optical Interferometry","authors":"N. Seliger, D. Pogany, C. Furbock, P. Habaš, E. Gornik, M. Stoisiek","doi":"10.1109/ESSDERC.1997.194478","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194478","url":null,"abstract":"Siemens Corporate Research and Development ZFE T KM6Otto-Hahn-Ring 6, D-81739 Munich, GermanyAbstract1. Introduction Silicon-On-Insulator (SOI) by Direct Wafer Bonding [1] has become an attractivetechnique for the fabrication of smart power devices. Self-heating effects in such structuresare, however, more critical compared to bulk devices due to a reduced heat removal acrossthe buried and trench oxides [2,3]. Power dissipation could cause localized temperatureincrease in the device active region, which may influence the device performance andreliability. In monolithic chip technology, the amount of heat laterally spread from the powerdevices across the sided trench oxides is also important as it may influence thecharacteristics of a nearby CMOS control circuit. In this paper we present an analysis of thetransient temperature variations inside and outside the SOI well of smart power devicesobtained by optical interferometry measurements. 2. Measurements The measurements have been carried out on trench isolated Lateral Double-diffused(LD)MOSFETs [4]. The SOI wafer structure consists of a highly doped p","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124619954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3