平面掺杂势垒场效应管:MOSFET克服了传统的限制

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI:10.1109/ESSDERC.1997.194506

W. Hansch, V. Rao, I. Eisele

{"title":"平面掺杂势垒场效应管:MOSFET克服了传统的限制","authors":"W. Hansch, V. Rao, I. Eisele","doi":"10.1109/ESSDERC.1997.194506","DOIUrl":null,"url":null,"abstract":"Introducing a concept of Electric-Field-Tailoring in vertical grown MOSFETs significant improvements concerning supply voltage, current and speed are possible. Based on vertical Silicon MOSFETs with sub-100nm channel lengths Planar-Doped-BarrierFETs were fabricated. Investigations on electrical characteristics and carrier transport show the predicted improvements compared to classical MOSFETs.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"The Planar-Doped-Barrier-FET: MOSFET Overcomes Conventional Limitations\",\"authors\":\"W. Hansch, V. Rao, I. Eisele\",\"doi\":\"10.1109/ESSDERC.1997.194506\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Introducing a concept of Electric-Field-Tailoring in vertical grown MOSFETs significant improvements concerning supply voltage, current and speed are possible. Based on vertical Silicon MOSFETs with sub-100nm channel lengths Planar-Doped-BarrierFETs were fabricated. Investigations on electrical characteristics and carrier transport show the predicted improvements compared to classical MOSFETs.\",\"PeriodicalId\":424167,\"journal\":{\"name\":\"27th European Solid-State Device Research Conference\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"27th European Solid-State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.1997.194506\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th European Solid-State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.1997.194506","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

在垂直生长的mosfet中引入电场剪裁的概念，可以显著改善电源电压，电流和速度。在沟道长度低于100nm的垂直硅mosfet的基础上，制备了平面掺杂势垒场效应管。对电特性和载流子输运的研究表明，与经典mosfet相比，预测的改进。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

The Planar-Doped-Barrier-FET: MOSFET Overcomes Conventional Limitations

Introducing a concept of Electric-Field-Tailoring in vertical grown MOSFETs significant improvements concerning supply voltage, current and speed are possible. Based on vertical Silicon MOSFETs with sub-100nm channel lengths Planar-Doped-BarrierFETs were fabricated. Investigations on electrical characteristics and carrier transport show the predicted improvements compared to classical MOSFETs.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

27th European Solid-State Device Research Conference

自引率

0.00%

发文量