{"title":"The Planar-Doped-Barrier-FET: MOSFET Overcomes Conventional Limitations","authors":"W. Hansch, V. Rao, I. Eisele","doi":"10.1109/ESSDERC.1997.194506","DOIUrl":null,"url":null,"abstract":"Introducing a concept of Electric-Field-Tailoring in vertical grown MOSFETs significant improvements concerning supply voltage, current and speed are possible. Based on vertical Silicon MOSFETs with sub-100nm channel lengths Planar-Doped-BarrierFETs were fabricated. Investigations on electrical characteristics and carrier transport show the predicted improvements compared to classical MOSFETs.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th European Solid-State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.1997.194506","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Introducing a concept of Electric-Field-Tailoring in vertical grown MOSFETs significant improvements concerning supply voltage, current and speed are possible. Based on vertical Silicon MOSFETs with sub-100nm channel lengths Planar-Doped-BarrierFETs were fabricated. Investigations on electrical characteristics and carrier transport show the predicted improvements compared to classical MOSFETs.