An Improved Technology for Elevated Source/Drain MOSFETS

In this paper the feasibility of an elevated source/ drain MOSFET technology which incorporates selective epitaxial growth of silicon, and does not suffer the technology problems of previously reported devices will be demonstrated. In our new device a layer of selective epitaxial silicon is grown in the source and drain regions of the MOSFET after sidewall spacer creation and before HDD implant. Some of the extra silicon is consumed during salicidation which will enable a thicker salicide to be grown to reduce parasitic source/ drain resistance, and the extra silicon will increase the planarity of the device. The new technology provides a higher quality of epitaxial seed crystal, hard masks the polysilicon gate during growth of selective epitaxial silicon, uses a thermal budget which is compatible with deep sub-micron CMOS, and e1iminates faceting of the epitaxial silicon.