27th European Solid-State Device Research Conference最新文献_第10页

GaAs Schottky Gate bipolar transistors for high voltage power switching applications 用于高压功率开关的GaAs肖特基栅双极晶体管

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194487

C. Johnson, M. Hossin, A. O'Neill

引用次数: 0

0.25 um NMOS transistor with nitride spacer: reduction of the short channel effect by optimisation of the gate reoxidation process and reliablity 带有氮化物间隔的0.25 um NMOS晶体管:通过优化栅极再氧化过程和可靠性来减少短通道效应

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194449

M. Ada‐Hanifi, M. Bonis, C. Verove, M. Basso, N. Revil, M. Haond, M. Lecontellec

{"title":"0.25 um NMOS transistor with nitride spacer: reduction of the short channel effect by optimisation of the gate reoxidation process and reliablity","authors":"M. Ada‐Hanifi, M. Bonis, C. Verove, M. Basso, N. Revil, M. Haond, M. Lecontellec","doi":"10.1109/ESSDERC.1997.194449","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194449","url":null,"abstract":"In this work, we present an investigation of the gate reoxidation step on the short channel effect. The thicker the thermal oxide, the stronger the roll-down of the threshold voltage on the NMOS transistor. This major result lead us to develop an alternative process for nitride spacer with the pad deposited TEOS that behaves as a convenient etch stop layer and allows to obtain a reduced short channel effect. The reliability results on NMOS transistor for the nitride spacers process are similar to those obtained with the TEOS spacer spacer. Introduction :Oxide spacers in deep sub-half micron technology are limited by a poor conformity of deposited oxides, trenching in the field oxide, and a high occurence of shunts between gate and drain or source, due to the salicidation step. Nitride spacers allow to overcome these difficulties, but usually require a thin oxide layer as etch stop of the nitride spacer etch, in order to prevent active area etch. In this study, it is demonstrated that the reoxidation after gate etch forms a bird's beak under the gate edges which induces an enhanced short channel effect. A thin TEOS deposited layer has been successfully used, in place of the thermal oxide, with the associated improvements of the device characteristics, in terms of short channel effect and Ion-Ioff trade-off optimisation. Process : 1/. In our CMOS 0.25mm process, 10 nm oxide is grown after gate etch and before LDD implants, this thickness is required to obtain a convenient etch stop for the nitride spacer etching. The thickness of the reoxidation was also checked for the TEOS spacer process. In this study, this thermal oxidation is compared with a TEOS oxide deposition of the same thickness 2/. Wet densification at 750°C is introduced after LDD Arsenic implantation in NMOS. This improves the oxide integrity before nitride spacer deposition and etch. Nitride spacer etch is performed in a LAM4428 using a standard plasma HBr-SF6-O2 chemistry. Uniformity is 4% and selectivity on oxide is 8. For 110 nm nitride deposition, the spacer width is 70 nm. For process comparison, this nitride spacer is compared to a 110 nm wide TEOS spacer. Results . Acomparison of oxide and nitride spacer process: In Figure 1, the variation of the NMOS threshold voltage (VT) versus the effective channel length does not show any difference between the nitride and the TEOS spacer in the NMOS devices. Since the series resistance is the same, we obtain the same ION-IOFF 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 0,15 0,25 0,35 0,45 Leff (μm) Fig.1 : VT(Leff) for nitride and TEOS spacer Nitride spacer TEOS spacer behaviour for oxide and nitride spacer devices : Figure 2. Moreover the channel length is the same, in each case. B Effect of the gate reoxidation on NMOS : TEOS spacers with a 5 nm thermal reoxidation indicate better performances than the above devices (10 nm reoxidation). Indeed, the VT(Leff) in Figure 3 indicates a reduction of the short channel effect and the ION-IOFF plot, given ","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131085406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Simulation of avalanche injection filamentation in MOSFET's and IGBT's MOSFET和IGBT中雪崩注入灯丝的模拟

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194429

V. Vashchenko, Y. Martynov, V. Sinkevitch

引用次数: 5

A Consistent Parameter Extraction Method for Deep Submicron MOSFETs 一种深亚微米mosfet参数一致提取方法

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194516

P. Klein

引用次数: 4

Technology of the Diode Programmable Read Only Memory 二极管可编程只读存储器技术

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194418

H. Lifka, P. Woerlee, C. de Graaf, C. Hart, P. Janssen, G. Paulzen, M. Theunissen, P. de Vreede

引用次数: 0

C-V characteristics of Pt/SrBi2Ta2O9/CeO2/Si structure for non-volatile memory devices 非易失性存储器件用Pt/SrBi2Ta2O9/CeO2/Si结构的C-V特性

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194539

H. Lee, D. Shin, Y.T. Kim, S. Choh

引用次数: 0

Analytical modeling of InP/InGaAs HBTs InP/InGaAs HBTs的分析建模

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194528

H. Sheng, A. Rezazadeh, D. Wake

引用次数: 0

Determination of interface state density of ULSI n-MOSFET by 1/f noise measurements 用1/f噪声测量法测定ULSI n-MOSFET的界面态密度

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194433

S. Villa, G. de Geronimo, A. Pacelli, A. Lacaita, A. Longoni

引用次数: 3

Optical testing of submicron-technology MOSFETs and bipolar transistors 亚微米技术mosfet和双极晶体管的光学测试

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194443

D. Pogany, C. Furbock, N. Seliger, P. Habaš, E. Gornik

引用次数: 3

A 0.5 um Flash Technology suitable for Low Voltage Embedded Applications 适用于低电压嵌入式应用的0.5 um闪存技术

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194415

J.K. Yeh, H. Su, Y. Lin, C.D. Shieh, D. Kuo, M. Liang, G. Tao, F. List, L. Shi, R. Colclaser, N. Tandan, K. Chen, M. Chen, A. Gorkum

引用次数: 2