J.K. Yeh, H. Su, Y. Lin, C.D. Shieh, D. Kuo, M. Liang, G. Tao, F. List, L. Shi, R. Colclaser, N. Tandan, K. Chen, M. Chen, A. Gorkum
{"title":"A 0.5 um Flash Technology suitable for Low Voltage Embedded Applications","authors":"J.K. Yeh, H. Su, Y. Lin, C.D. Shieh, D. Kuo, M. Liang, G. Tao, F. List, L. Shi, R. Colclaser, N. Tandan, K. Chen, M. Chen, A. Gorkum","doi":"10.1109/ESSDERC.1997.194415","DOIUrl":null,"url":null,"abstract":"High density, low supply voltage, low power consumption and fast program/erase flash memory are important in data storage for applications in portable electronic products. In this paper we present a 0.5 um low voltage flash technology embedded in a standard 0.5 um Ti-salicide logic process. Stacked gate flash memory cell is chosen and both programming and erase are done through by bi-directional Fowler-Nordheim tunneling. Single cell programming and erasing times are 5ms and 10ms, respectively. With page mode programming, a programming time of 5us per bit are achieved. The single cell endurance is better than 10 cycles.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th European Solid-State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.1997.194415","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
High density, low supply voltage, low power consumption and fast program/erase flash memory are important in data storage for applications in portable electronic products. In this paper we present a 0.5 um low voltage flash technology embedded in a standard 0.5 um Ti-salicide logic process. Stacked gate flash memory cell is chosen and both programming and erase are done through by bi-directional Fowler-Nordheim tunneling. Single cell programming and erasing times are 5ms and 10ms, respectively. With page mode programming, a programming time of 5us per bit are achieved. The single cell endurance is better than 10 cycles.