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A new structure for reduction of the leakage currrent in the low temperature Poly-Si TFTs fabricated by the MILC process 采用MILC工艺制备的低温多晶硅tft中，一种降低泄漏电流的新结构
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194503
T. Ihn, B. Lee, S. Joo
{"title":"A new structure for reduction of the leakage currrent in the low temperature Poly-Si TFTs fabricated by the MILC process","authors":"T. Ihn, B. Lee, S. Joo","doi":"10.1109/ESSDERC.1997.194503","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194503","url":null,"abstract":"Poly-Si TFTs were fabricated at 500 t' by a Ni offset metal induced lateral crystallization(MILC) method. The poly-Si TFTs fabricated by the Ni offset MILC showed lower leakage current than those fabricated by conventional Ni self aligned MILC without sacrifice of field eff ect mobility. The decrease of leakage current resulted from the exclusion of Ni rich phase at near the","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125311276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
18 GHz high gain monolithically integrated InP/InGaAs PIN/HBT-Receiver 18ghz高增益单片集成InP/InGaAs PIN/ hbt接收机
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194423
D. Huber, M. Bitter, R. Bauknecht, T. Morf, C. Bergamaschi, H. Jackel
{"title":"18 GHz high gain monolithically integrated InP/InGaAs PIN/HBT-Receiver","authors":"D. Huber, M. Bitter, R. Bauknecht, T. Morf, C. Bergamaschi, H. Jackel","doi":"10.1109/ESSDERC.1997.194423","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194423","url":null,"abstract":"We report on the design, fabrication and characterization of a monolithically integrated InP/InGaAs PIN/HBT-Photoreceiver for a wavelength of . Base and collector layers of the HBT have been used to implement the photodiodes. The three-stage-amplifi erachieves a transimpedance of ( ) and the optical/electrical -bandwidth of the entire receiver is . This corresponds to a transimpedancebandwidth product of , which is one of the highest values published to date.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122883546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Development of the Next Generation of Insulated Gate Bipolar Tranistors based on Trench Technology 基于沟槽技术的新一代绝缘栅双极晶体管的研制
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194476
F. Udrea, S.S.M. Chan, J. Thomson, S. Keller, G. Amaratunga, A. Millington, P. Waind, D. Crees
{"title":"Development of the Next Generation of Insulated Gate Bipolar Tranistors based on Trench Technology","authors":"F. Udrea, S.S.M. Chan, J. Thomson, S. Keller, G. Amaratunga, A. Millington, P. Waind, D. Crees","doi":"10.1109/ESSDERC.1997.194476","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194476","url":null,"abstract":"This paper presents preliminary results towards developing the next generation of Insulated Gate Bipolar Transistors for high voltage applications. Technological issues such as the trench profile, the gate oxide quality, the trench inversion layer mobility and lay-out design are discussed. Optimization of 1.8 kV Trench IGBTs using extensive numerical simulations and physical analysis is carried out. New termination techniques are proposed.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116869591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Optimisation of Ultra High Density MOS Arrays in 3Ds 3Ds中超高密度MOS阵列的优化
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194417
T. Haneder, E. Bertagnolli, H. von Philipsborn, W. Krautschneider, F. Hofmann, J. Willer, T. Boehm
{"title":"Optimisation of Ultra High Density MOS Arrays in 3Ds","authors":"T. Haneder, E. Bertagnolli, H. von Philipsborn, W. Krautschneider, F. Hofmann, J. Willer, T. Boehm","doi":"10.1109/ESSDERC.1997.194417","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194417","url":null,"abstract":"","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122042975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new cellular etching-simulator for InP and Si 一种新型的InP和Si细胞蚀刻模拟器
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194470
H. Wehmann, M. Chahoud, A. Schlachetzki
{"title":"A new cellular etching-simulator for InP and Si","authors":"H. Wehmann, M. Chahoud, A. Schlachetzki","doi":"10.1109/ESSDERC.1997.194470","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194470","url":null,"abstract":". A simple etching simulator is presented that combines the advantages of geometrical and cellular models. The simulator is based on a cell representation of the crystal. The cells at the etching front are deterministically removed or remain in the crystal depending on the experimentally determined etching rates. We compare InP patterns etched in HBr and Si structures from the literature with simulated results. Although in the simulation only low indexed planes were taken into account higher index planes emerge at complex structures.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116905258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Lateral Channel Doping Engineering in 0.1um Recessed Channel nMOSFETs 0.1 m凹槽nmosfet的横向沟道掺杂工程
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194409
J. Lyu, Y. Choi, B. Park, K. Chun, J.D. Lee
{"title":"Lateral Channel Doping Engineering in 0.1um Recessed Channel nMOSFETs","authors":"J. Lyu, Y. Choi, B. Park, K. Chun, J.D. Lee","doi":"10.1109/ESSDERC.1997.194409","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194409","url":null,"abstract":"Many researchers have reported the characteristics of 0.1μm nMOSFETs using vertical channel doping engineering[1] and drain engineering in planar and groove gate(elevated S/D)[2] structures. But there has not been an extensive study on the channel doping engineering in the lateral direction of 0.1μm channel length. In this paper, by simulation and fabrication, we have shown that the laterally graded channel doping profile has a strong influence on the device performance and short channel effect in 0.1μm recessed channel structure for the first time.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127567406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 73 GHz SiGe SIMMWIC module 一个73 GHz SiGe SIMMWIC模块
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194532
K. Strohm, F. Beisswanger, J. Luy
{"title":"A 73 GHz SiGe SIMMWIC module","authors":"K. Strohm, F. Beisswanger, J. Luy","doi":"10.1109/ESSDERC.1997.194532","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194532","url":null,"abstract":"Active SIMMWIC antennas with two terminal impact avalanche transit time (IMPATT) diodes have been realized. Frequency stabilization and frequency modulation of these active antennas is realized by subharmonic injection locking using a SiGe HBT oscillator. For this the 73 GHz active antenna is combined with a 24.4 GHz SiGe HBT oscillator. Synchronization is achieved at the third harmonic. Frequency modulation of 137 MHz is observed","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117037718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Investigation of the influence of impact ionization feedback on the spatial distribution of hot carriers in an NMOSFET 碰撞电离反馈对NMOSFET中热载流子空间分布影响的研究
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194434
C. Jungemann, S. Yamaguchi, H. Goto
{"title":"Investigation of the influence of impact ionization feedback on the spatial distribution of hot carriers in an NMOSFET","authors":"C. Jungemann, S. Yamaguchi, H. Goto","doi":"10.1109/ESSDERC.1997.194434","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194434","url":null,"abstract":"It is demonstrated with full-band Monte Carlo simulations that the spatial distribution of hot carriers generated by impact ionization feedback differs considerably from the one of the primary particles. Especially the distribution of hot electrons at the Si/SiO2-interface is broadened under the influence of a back bias and this spatial change of the hot electron injection into the interface might result in a different device degradation behaviour.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116490051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Novel Diffusion Coupled Oxidation Model 一种新的扩散耦合氧化模型
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194468
M. Radi, E. Leitner, E. Hollensteiner, S. Selberherr
{"title":"A Novel Diffusion Coupled Oxidation Model","authors":"M. Radi, E. Leitner, E. Hollensteiner, S. Selberherr","doi":"10.1109/ESSDERC.1997.194468","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194468","url":null,"abstract":"A new approach to the three-dimensional local oxidation of silicon is presented, that is based on a parameter dependent smooth transition zone between silicon and sili­ con dioxide. The resulting two phase problem is solved by calculating a free diffusive oxygen concentration, which reacts with unsaturated silicon to silicon dioxide. This chemical reaction causes a volume dilatation which leads to mechanical stress con­ cerning the surrounding boundary conditions. By a suitable set of parameters this kind of approach is equivalent to the standard sharp interface model based on the fundamental work of Deal and Grove. The main advantage is, that the mesh remains topologically invariant during the progress of oxidation and therefore no remeshing is necessary.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116530744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Mechanisms of Localized Charge Injection: A Technique to Characterize Gate Edge Damage in MOS Transistors 局域电荷注入机制:MOS晶体管栅极边缘损伤表征技术
27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI: 10.1109/ESSDERC.1997.194490
A. Sridharan, V. Rao, T. Brożek, J. Werking, C. Viswanathan
{"title":"Mechanisms of Localized Charge Injection: A Technique to Characterize Gate Edge Damage in MOS Transistors","authors":"A. Sridharan, V. Rao, T. Brożek, J. Werking, C. Viswanathan","doi":"10.1109/ESSDERC.1997.194490","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194490","url":null,"abstract":"In this paper we discuss the detailed mechanism of Localized Charge Injection (LCI) technique which was proposed recently to characterize gate edge damage and gate oxide thickening in deep submicron MOS transistors. Under the condition of large reverse voltage applied between the gate and drain with channel biased in accumulation, we show from experimental and 2-D device simulation results that charge injection into the gate oxide will be localized only at the gate-drain overlap region. The ga�e voltage required to sustain this localized charge injection will be shown in this work as being extremely sensitive to the edge oxide thickness and can be used as a measure of plasma edge damage which occurs during processing.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131689079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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