K. Mouthaan, R. Tinti, A. Arno, H. de Graaff, J. Tauritz, J. Slotboom
{"title":"Thermal resistance modelling of RF high power bipolar transistors","authors":"K. Mouthaan, R. Tinti, A. Arno, H. de Graaff, J. Tauritz, J. Slotboom","doi":"10.1109/ESSDERC.1997.194396","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194396","url":null,"abstract":"Thermal modelling of RF high power bipolar transistors including the ther mal resistance of the silicon die and the beryllium oxide package as well as the temperature dependence of their thermal conductivities is considered To model power transistors the non linear heat conduction equation is con verted to a linear heat equation using Kirchho s transformation The linear problem is solved using a Green s function method and the Kirchho transformation is e ectuated via a non linear voltage transformation Introduction RF high power transistors are used in base stations for mobile radio radar and satellite com munications to amplify signals to a power level of a few Watts or more Basically these devices consist of a package one or more matching capacitances bonding wires and a silicon die The silicon Si die has a number of active areas and each active area has a number of base and emitter ngers The accurate modelling of the thermal behaviour is of particular relevance since the tem perature in uences the electrical behaviour of the transistor and plays an important role in determining the safe operating area SOA of the device Several methods such as the Finite Element Method FEM and the Finite Di erence Time Domain method FDTD can be used to calculate the temperature at the junction of the devices These methods easily incorporate the temperature dependence of the thermal conduc tivity of the materials involved Simulation times however can be in the order of minutes or hours for the accurate modelling of practical problems Dramatic time savings can be achieved when Green s function methods are employed A principal drawback of this approach is that it fails to incorporate the temperature dependence of the thermal conductivity so that the method is limited to linear problems In this work a robust and e cient implementation of a method for calculating the temper ature distribution and the thermal resistance matrix in Hewlett Packard s Microwave Design System MDS is demonstrated The method is based on proper splitting of the thermal prob lem in a linear problem solved using a Green s function method followed by a non linear Kirchho transformation This division is advantageous in that we obviate the need to recom pute the thermal matrix at every simulation point as is done for example in Simulation times for practical problems are in the order of seconds making the method amendable to CAD applications Computation of the thermal resistance matrix In the thermal model the Si die is placed on top of the beryllium oxide BeO substrate of the package as illustrated in gure The BeO substrate is on top of the mounting base which is maintained at a constant reference temperature Junctions are located in the active areas just below the surface of the Si die where heat is generated due to power dissipation","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123591513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Gatti, A. Longoni, G. de Geronimo, Angelo Geraci
{"title":"A new numerical method for determining the excess noise power spectrum in MOSFETs","authors":"E. Gatti, A. Longoni, G. de Geronimo, Angelo Geraci","doi":"10.1109/ESSDERC.1997.194432","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194432","url":null,"abstract":"This work deals with the evaluation of the low frequency noise spectrum associated to the random capture and release of carriers by localized traps in MOSFETs. The proposed numerical method, based on the linearization of the semiconductor device equations, is applicable in any biasing condition and for any position and activation energy of the traps inside the device. The experimental validation of the procedure has been performed and first results are here presented.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123855684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Statisitcal Analysis for IC-Management","authors":"V. Axelrad, J. Kibarian","doi":"10.1109/ESSDERC.1997.194391","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194391","url":null,"abstract":"Increasing circuit complexity and die area with at the same time decreasing device dimensions render traditional approaches to IC design inadequate. The result is serious risk of suboptimal designs and thus poor performance and/or poor manufacturing yield. New tools are necessary to capture the effects of statistical variability of devices and interconnects on circuit performance. No longer can circuit design be carried out independently of the process design as interactions between the two cannot be neglected. This means redefining the conventional Mead-Conway design style which has served the industry so well in the past. A new design-manufacturing interface is described and a few challenges and solutions are shown.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130419506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Candelier, B. De Salvo, F. Martin, B. Guillaumot, F. Mondon, G. Reimbold
{"title":"Thinning Oxide-Nitride-Oxide Interpoly Dielectric (11-13nm) for 0.25 um Flash Cell Memories","authors":"P. Candelier, B. De Salvo, F. Martin, B. Guillaumot, F. Mondon, G. Reimbold","doi":"10.1109/ESSDERC.1997.194416","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194416","url":null,"abstract":"","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129375930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Stategic Alliances for highly efficient 300 mm Waferfabs","authors":"J. Giessmann","doi":"10.1109/ESSDERC.1997.194390","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194390","url":null,"abstract":"State-of-the-Art waferfabs require a growing demand for integrated and highly efficient system solutions in terms of investment costs, running costs and yield improvement. It will be explained which factors are determinant to the profitability of a waferfab. Making the change from 200 mm to 300 mm wafers together with the jump to 0.25 μm technology will be the challenge the entire semiconductor industry within the coming years. The author explains why the jump to 300 mm is so critical in terms of technology and efficiency. The investment costs which are necessary to cope with the 300 mm challenge are more than any single company can handle. This is why strategic alliances have to be founded. The impacts are obvious: Systems or turnkey supplier to the semiconductor industry have to contribute as well as the chipmanufacturers to ease the burden of huge investment costs. 1. Growing Demands of the Industry in Terms of Investment Costs, Running Costs and Yield Improvement Investment costs as well as running costs of a fab increase tremendously. See fig. 1. Fig. 1 IC Facility Costs Page 1/7 2. The 300 mm Transition At Semicon/Japan 1995 the world s IC-producing nations agreed that 300 mm should be the next generation of silicon wafer size. At that time the production of these larger diameter wafers was expected to start in 1998. The conversion to 300 mm wafers is expected to lead to a significant reduction in manufacturing costs, improve yields and enable other productivity improvements. Regarding to six major factors the start up for production in 1998 seems to be too optimistic: Larger development times, extended wafer life cycles, market situation, materials shortages, technical obstacles and funding issues. The transitions to 150 mm and 200 mm respectively were funded in both cases by one single company. Regarding to the increased huge investment and developing costs no single company is willing and able to pay for the transition. The development time for a new wafer generation has increased significantly (see fig. 2). Fig.2. Wafer Development Time It has been estimated that it will cost the global semiconductor industry and its suppliers as much as US$ 14 billion to develop a 300 mm capability by the end of the decade. So, why is the industry making such an enormous effort ? The transition into 300 mm technology is merely driven by economics. The number of dies per wafer will increase by the factor 2,4 to 2,7. Big logic devices require bigger wafer diameter and thus increase die per wafer efficiency. See fig.3. For large CPU chips with 5 to 10 M transistors the efficiency on 300 mm wafers is higher. See fig.3. The cost per die is expected to be 25 40 % lower. Finally there are fewer fabs necessary to be built to meet the demand for chips. The 300 mm transition is going to increase investment costs and running costs for waferfabs. On the other hand, chip productivity increases with respect to the wafersizes.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129805359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Inoh, H. Nii, S. Yoshitomi, C. Yoshino, H. Furuya, H. Nakajima, H. Sugaya, H. Naruse, Y. Katsumata
{"title":"Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure","authors":"K. Inoh, H. Nii, S. Yoshitomi, C. Yoshino, H. Furuya, H. Nakajima, H. Sugaya, H. Naruse, Y. Katsumata","doi":"10.1109/ESSDERC.1997.194482","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194482","url":null,"abstract":"In this paper, we demonstrate that the sidewall spacer thickness of double polysilicon self-aligned bipolar transistor structure is one of the fundamental limitations in bipolar transistor scaling by using an accurate small signal equivalent circuit. The simulated results show that the maximum fT reduces to half when the sidewall spacer thickness reduces from 0.1μm t o 0.025μm.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124420460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Finite Element Analysis of Stress Distributions in Interconnect Structures","authors":"J. Coughlan, S. Foley, Alan Mathewson","doi":"10.1109/ESSDERC.1997.194463","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194463","url":null,"abstract":"Finite element analysis has been used to study the influences of different inter metal dielectric materials, via plug-fill technologies and material properties on the thermal-mechanical stresses in a two level interconnect structure. Results indicate the presence of large stresses and stress gradients at metal interfaces which could lead to delamination failures and have a detrimental effect on the electromigration performance of an interconnect system.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115263231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparison of an L-array and a single transistor method to extract Leff and Rs in deep submicron MOSFETs","authors":"S. Biesemans, K. De Meyer","doi":"10.1109/ESSDERC.1997.194515","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194515","url":null,"abstract":"","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131377472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Christoph Kopf, G. Kaiblinger-Grujin, H. Kosina, S. Selberherr
{"title":"Reexamination of Electron Mobility Dependence on Dopants in GaAs","authors":"Christoph Kopf, G. Kaiblinger-Grujin, H. Kosina, S. Selberherr","doi":"10.1109/ESSDERC.1997.194426","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194426","url":null,"abstract":"The influence of dopant species on electron mobility in GaAs is investigated. Based on Thomas-Fermi theory to describe the charge density of the individual impurity ion we derive an analytical expression for the scattering rate. Employing these results in a Monte Carlo calculation we fi nda signifi cantdependence of mobility on donor species for concentrations beyond cm . With increasing concentration an increasing difference is observed, ions with larger atomic number lead to lower mobility values. In case of minority electron mobility no signifi cantdopant dependence is predicted.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130606400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}