27th European Solid-State Device Research Conference最新文献

{"title":"Study of pocket implant parameters for 0,18 um CMOS","authors":"J. Schmitz, Y. Ponomarev, A. Montree, P. Woerlee","doi":"10.1109/ESSDERC.1997.194406","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194406","url":null,"abstract":"PMOS and NMOS transistors for the 0.18 μm CMOS generation with pocket punch-through stoppers are presented. A detailed study of the dose and angle of the pocket implants is presented, showing that these implant conditions do not affect the long-channel S and VT, nor the substrate current. A clear optimum is found when threshold voltage rolloff and subthreshold swing are evaluated, leading to the best performance in terms of Ion/Ioff ratio.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121045346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Source/Drain Engineering with Ge Large Angle Tilt Implantation and Pre-Amorphization to Improve Currrent Drive and Alleviate Floating Body Effects of Thin Film SOI MOSFETs","authors":"T. Hsiao, P. Liu, W. Lynch, J. Woo","doi":"10.1109/ESSDERC.1997.194479","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194479","url":null,"abstract":"This work presents an advanced salicide technology for thin film SiliconOn-Insulator (SOI) MOSFET s. Germanium large angle tilt implantation is applied to amorphize the silicon films prior to silicidation. This novel salicide technology greatly reduces the silicide formation energy and effectively controls the silicide depth. As a result, source/drain parasitic resistances are substantially reduced. In addition, due to the formation of a metal semiconductor barrier near the source/channel junction, the floating body effects are alleviated. fabricated using Ge pre-amorphization [1] [2]. A lower silicide formation thermal cycle is chosen so that the silicide is formed within the amorphous layer. The I-V characteristics of two different salicide processes with 0.3 μm effective channel lengths are shown in Fig. 1. Process flow for Ge pre-amorphization is also included. In addition to reducing source/drain resistance, Ge implantation improves the breakdown characteristics. Fig. 2 shows the measured breakdown voltage versus effective channel length for SOI devices with TSOI equal to 90 nm. Devices with Ge implantation increase the breakdown voltage by 0.3 V compared to devices without Ge implantation. In this work, a large angle Ge implantation was used to amorphize the silicon","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121053794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25um (n+/p+) Dual-Workfunction CMOS Technology","authors":"U. Schwalke, J. Berthold, A. Bourenkov, M. Eisele, R. Krieg, A. Narr, D. Schumann, R. Seibert, R. Thanner","doi":"10.1109/ESSDERC.1997.194405","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194405","url":null,"abstract":"1 2 & The decrease in supply voltage is the most effective approach to reduce power consumption in CMOS circuits. Accordingly, the ultimate goal for many low-power applications is aimed at a single-battery operation with a nominal supply voltage of 1.2V and an end-of-life voltage of 0.9V. On the other hand, circuit performance is often sacrified when supply voltage (Vdd) is reduced. In order to compensate for the loss in drive current, threshold voltage (Vth) is reduced. This approach, however, requires an n+/p+ gate technology /1/ with optimized gate workfunction for Nand PMOS devices to achieve sufficient performance at low voltage and still maintain good short channel behavior as well as low off-leakage (Ioff).","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128373343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Three-Dimensional Simulation of Contact Hole Metallization using Aluminum Sputter Deposition at Elevated Temperatures","authors":"E. Bear, J. Lorenz, H. Ryssel","doi":"10.1109/ESSDERC.1997.194469","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194469","url":null,"abstract":"A three dimensional D simulation program has been developed which is capable of simulating layer deposition on D geometries In this paper we present the application of the tool to the simulation of aluminum sputter deposition at elevated temperatures It is assumed that due to the higher temperature surface di usion of the atoms is possible In consequence the step coverage is better than for cold sputter deposition To model surface di usion a transport coe cient K is introduced as parameter which can be related to the di usion length Simulation results for di erent values of K are shown It turned out that if K is far larger than the dimension of the contact hole void free lling of the hole is achieved Introduction Current and future generations of integrated circuits require processes capable of lling high aspect ratio contact holes and vias Conventional sputtering at low temperature leads to only poor step coverage resulting in incomplete lling of the contact holes and vias This problem gets worse as the aspect ratios of the holes increase Thus speci c techniques have to be developed which are suitable for lling the holes One possibility is to carry out the sputtering process at an elevated temperature allowing surface di usion of the metal atoms before they are incorporated into the growing layer In consequence the atoms are distributed more uniformly over the entire structure leading to improved contact ll Model and D Implementation In this paper we present an approach to model surface di usion during re ow sputtering at elevated temperatures For this purpose a D simulator which had originally been developed for the simulation of low pressure chemical vapor deposition LPCVD processes was extended In LPCVD simulation particles from gas space which hit the surface are incorporated into the growing layer with a certain probability the so called sticking coe cient For sputter deposition a sticking coe cient equal to can be assumed i e no desorption of the metal atoms from the surface takes place The geometry is described by a set of triangles which are shifted according to the growth rates calculated from the particle ux of atoms arriving from the gas volume at this triangle To include surface di usion particle transport between neighboring triangles i e between triangles with one side in common has to be taken into account A transport coe cient K depending on temperature and process time is introduced as the model parameter The rate of particle exchange between neighboring triangles is proportional to K It has been shown that the di usion length is of the same order of magnitude as K For each surface triangle a dynamical equilibrium between positive and negative particle uxes is assumed The positive uxes are due to particles arriving from the gas volume or neighboring triangles the negative uxes are due to particle consumption by incorporation into the growing lm or due to particles di using to neighboring triangles The corresponding equations are","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129716425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A fully GaAs-based 100MHz, 2W DC-to-DC Power Converter","authors":"S. Ajram, R. Kozlowski, H. Fawaz, D. Vandermoere, G. Salmer","doi":"10.1109/ESSDERC.1997.194421","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194421","url":null,"abstract":"Potential applications of III-V power devices in the very highfrequency, high-efficiency and compact size DC-to-DC switching converters are shown. A 100MHz-5V/10V-2W Boost converter, fully based on GaAs semiconductors, is presented. A specific 27V breakdown Schottky rectifier has been realised for this purpose as well as a 500ps transition time MESFET-based gate driver. Power efficiency of about 69% has been reached.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130946425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of processing temperatures on device design rules for Silicon/Silicon Germanium heterojunction bipolar transistors","authors":"R. Bashir, A. Kabir, E. R. Myers, J. DeSantis, C. Bracken, P. Westrom, F. Wang","doi":"10.1109/ESSDERC.1997.194440","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194440","url":null,"abstract":"","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114509650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Stress Technique Suitable For The In-Line Reliability Monitoring Of The Hot Carrier Endurance of Sub-0,5um MOSFETs","authors":"C. Dimitriadis, C. Papadas, A. Concannon, N. Villani, E. Vincent, A. Mathewson","doi":"10.1109/ESSDERC.1997.194497","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194497","url":null,"abstract":"The purpose of this paper is to present a stress mode which allows the hot carrier endurance of sub-half micron MOSFETs to be evaluated within 100s of DC stress. Contrary to the classical approach which requires substantially longer test times (i.e. about 10s of DC stress at the maximum substrate current), the proposed technique is suitable for in-line reliability monitoring applications.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116318633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Measurement of Channel Length and Off-set Region Length for Off-set Gate MOSFETs","authors":"K. Terada, K. Tsuji, Y. Itoh, M. Takahashi","doi":"10.1109/ESSDERC.1997.194513","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194513","url":null,"abstract":"This paper proposes an extraction method of both the channel length and the off-set region length, which is defined as the channel length of the JFET formed there, for off-set gate MOSFETs. The influence of MOSFET in the JFET current measurement is removed by extrapolating the gate bias of the MOSFET to infinity. Experimental data confirm that this extraction method can accurately determine both channel lengths.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"349 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132245774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi Layer Metallization","authors":"M. Lerme","doi":"10.1109/ESSDERC.1997.194378","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194378","url":null,"abstract":"Scaling down of interconnect will increase circuit density at the detriment of performance if no improvement in both design and technology are introduced. Consequently, new materials improving this interconnect performance will be introduced such as conductor with lower resistivity compared to aluminum alloys and dielectric with lower ε compared to silicon oxide as well as new architecture for integration.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133754319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A performance comparison between 0.35um self-aligned and quasi-self-aligned double-polysilicon bipolar transistors","authors":"L. Ailloud, J. de Pontcharra, G. Bartoletti, J. Kirtsch, G. Auvert, A. Chantre","doi":"10.1109/ESSDERC.1997.194453","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194453","url":null,"abstract":"This paper reports a performance comparison between self-aligned (SA) and quasi-self-aligned (QSA) double-polysilicon bipolar transistors fabricated on the same wafer. A novel technique for forming the link base of QSA devices has been developed, which allows to obtain good static and dynamic performances.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133490519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}