Realization and Evaluation of an Ultra Low-Voltage/Low-Power 0.25um (n+/p+) Dual-Workfunction CMOS Technology

1 2 & The decrease in supply voltage is the most effective approach to reduce power consumption in CMOS circuits. Accordingly, the ultimate goal for many low-power applications is aimed at a single-battery operation with a nominal supply voltage of 1.2V and an end-of-life voltage of 0.9V. On the other hand, circuit performance is often sacrified when supply voltage (Vdd) is reduced. In order to compensate for the loss in drive current, threshold voltage (Vth) is reduced. This approach, however, requires an n+/p+ gate technology /1/ with optimized gate workfunction for Nand PMOS devices to achieve sufficient performance at low voltage and still maintain good short channel behavior as well as low off-leakage (Ioff).