{"title":"多层金属化","authors":"M. Lerme","doi":"10.1109/ESSDERC.1997.194378","DOIUrl":null,"url":null,"abstract":"Scaling down of interconnect will increase circuit density at the detriment of performance if no improvement in both design and technology are introduced. Consequently, new materials improving this interconnect performance will be introduced such as conductor with lower resistivity compared to aluminum alloys and dielectric with lower ε compared to silicon oxide as well as new architecture for integration.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Multi Layer Metallization\",\"authors\":\"M. Lerme\",\"doi\":\"10.1109/ESSDERC.1997.194378\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Scaling down of interconnect will increase circuit density at the detriment of performance if no improvement in both design and technology are introduced. Consequently, new materials improving this interconnect performance will be introduced such as conductor with lower resistivity compared to aluminum alloys and dielectric with lower ε compared to silicon oxide as well as new architecture for integration.\",\"PeriodicalId\":424167,\"journal\":{\"name\":\"27th European Solid-State Device Research Conference\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"27th European Solid-State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.1997.194378\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th European Solid-State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.1997.194378","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Scaling down of interconnect will increase circuit density at the detriment of performance if no improvement in both design and technology are introduced. Consequently, new materials improving this interconnect performance will be introduced such as conductor with lower resistivity compared to aluminum alloys and dielectric with lower ε compared to silicon oxide as well as new architecture for integration.