27th European Solid-State Device Research Conference最新文献

{"title":"Performance limits of deep submicron buried channel delta doped MOSFETs","authors":"K. Diawuo, A. O'Neill","doi":"10.1109/ESSDERC.1997.194511","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194511","url":null,"abstract":"","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127871676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of high temperature on performances and hot-carrier reliability in DC/AC stressed 0.35 um n-MOSFETs","authors":"A. Bravaix, D. Goguenheim, N. Revil, M. Varrot, P. Mortini","doi":"10.1109/ESSDERC.1997.194496","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194496","url":null,"abstract":"!\"#$%&!'# The studies on hot-carrier reliability are usually achieved at room temperature (RT) or at low temperature [1,2] as the hot-carrier degradation has generally more impact on the device characteristics at these temperatures than at high temperature (HT). Only few works deal with channel hot-carrier injections and transistor performances at HT in n-MOSFET’s [3,4,5] which must be evaluated for scaling-down technologies as circuits operate over a wide range of temperature. One of the primary reason is the reduced electron mobility and the reduction of the number of high energy carriers able to create damage. The major consequence is that the substrate and gate currents both decrease at HT [4-6] which is mainly caused by an increased mean free path of channel electrons and a reduced channel electric-field at HT. Hence it is expected that the influence of the interface trap generation and the charge trapping in the gate-oxide is reduced at HT. However the degradation of n-MOSFET’s at HT has gained new interests [3] due to the enhanced degradation of the saturation drain current observed in a 0.55-0.65μm LDD CMOS technology. It is generally accepted that the mechanism of interface trap generation is temperature independent using experiments in the 77-295°K range [2] pointing out the effect of the temperature itself on the device characteristics. In this work the impact of HT is studied on the transistor parameters and on the hot-carrier reliability during digital operation.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128822217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Silicon Microsystems for Automotive Applications","authors":"J. Marek","doi":"10.1109/ESSDERC.1997.194383","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194383","url":null,"abstract":"The integration of microelectronic and micromechanical devices into one system the microsystem technology is rapidly gaining importance in automobiles. According to market studies the content of electronics as well as of microsystems in automobiles is increasing more than proportionally. The major driving forces are the environmental requirements, safety and comfort. The microsystem technology contributes in these areas due to the reduction of costs, weight and size as well as improved reliability and functionality. Sensor systems for the measurement of manifold air intake pressure, mass flow, acceleration for ABS and airbag and yaw rate will be discussed in detail. In the nineties a new technology, the surface micromachining, is emerging. This technology is being made available to small and medium size companies as well as to universities and research institutes by a foundry-service-scheme sponsored by the European Union.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"448 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116331840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Piezoresistive bridge configuration for atomic force microscopy","authors":"R. Jumpertz, A. van der Hart, J. Schelten, O. Ohlsson, T. Sulzbach, F. Saurenbach","doi":"10.1109/ESSDERC.1997.194520","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194520","url":null,"abstract":"","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126307963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal analytical model for analysis of pulsed DC electromigration results","authors":"P. Waltz, G. Lormand, L. Arnaud","doi":"10.1109/ESSDERC.1997.194471","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194471","url":null,"abstract":"Thermal calculations have been performed in order to evaluate the real operating temperature of an interconnection during a pulsed current stress. The developed thermal model gives a good approximation of the average temperature needed for the exploitation of pulsed electromigration tests, in function of the stress parameters : frequency, duty cycle and current density. Electrical measurements on single level AlCu metallization allowed us to verify the model and to point out some thermal effects in the high frequency region. Introduction In order to exploit electromigration results with the Black s equation [1] , the knowledge of the temperature of the failure site is needed. During DC tests, this temperature is considered being the average temperature of the line, is assumed to be constant and is calculated through resistance measurements. The problem becomes more complex when periodic currents are applied to the sample. Some authors have already faced this problem during their pulsed EM studies [2-4]. Hereafter, we develop a simple thermal model which allows us to calculate more precisely the real sample temperature in the case of unidirectional current pulses and which can be applied to bi-directional current stresses. Thermal model Our thermal model describes the sample as a first order system, which means the use of one thermal time constant [2,3]. This hypothesis has been verified via 2D simulations using a finite elements method. A purely resistive line is submitted to a periodic Joule heating. The power P(t) dissipated during the time interval dt is equal to the accumulated heat added to thermal losses (Equation 1). • P(t)dt dT (T T )dt s = + − α β (1) Ts : Substrate temperature α, β : Constants For one power step with a peak value P0, Equation 1 can easily be solved by assuming that T=T0 for t=0 : • T(t) T exp( )( exp( = − − − 0 1 β α β β α t) + ( P + T t)) 0 S (2) where α is the thermal capacitance, 1/β the thermal resistance. Thus the thermal time constant of the sample is : τth= α/β=Cth.Rth In the following, we set down Ts=0°C, DTm=P0/b. ∆Tm is then the DC Joule heating of the sample. By applying square power pulses, the temperature of the sample reaches a periodic regime and evolves in a temperature interval [T1 ; T2] defined by the stress conditions and the thermal time constant. Figure 1 shows the plot of Temperature vs Time for 2 values of τth at steady state.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123591909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rapid IC Performance Yield and distribution prediction using a rotation of the circuit parameter principals components","authors":"J. Horan, C. Lyden","doi":"10.1109/ESSDERC.1997.194512","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194512","url":null,"abstract":"Abstract Monte-Carlo techniques for prediction of IC yield in the presence of inter-die parameter variations are well established in the literature [Luigi P. Monte-Carlo simulation of semiconductor device and process modelling; critical review. IEEE Trans CAD 1990; CAD-9: 1164--76], but their use in commercial design is limited by their high computational cost. This paper presents a novel technique which shows a great reduction in the simulation cost and sustains the accuracy. It does this by first using Principal Component Analysis (PCA) [Cureton EE et al. Factor analysis: an applied approach. Hillsdale, New Jersey: Laurence Erlbaum Associates, 1983] to identify the significant orthogonal directions of variation in the process space. The next steps involve the development of an accurate approximation of the two dimensional yield boundary. Finally, an analytic integration in the process space provides the yield. The steps involved in the yield calculation also conveniently produce performance distributions and this is described.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122634864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Detailed Matching Analysis of Sub-50 nm-MOS-Transistors","authors":"J. Horstmann, U. Hilleringmann, K. Goser","doi":"10.1109/ESSDERC.1997.194410","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194410","url":null,"abstract":"The local and global matching of NMOS-transistors with dimensions from W/L = 10 μm/1 μm down to W/L = 1 μm/30 nm is analyzed by a large number of measurements. Results are compared to simulations, verifying the law of area (σV W L T ∝ ⋅ 1 / ) even for smallest geometries. Except the transistors with a gatelength of 1 μm all transistors are structured by a depositionand etchback technique giving an excellent homogeneity and reproducibility in linewidth. Finally proceedings to avoid the increasing mismatch with decreasing channel area will be discussed.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131414490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Unified Approach for Modeling Multiterminal Bipolar and MOS Devices in Smart-Power Technologies","authors":"N. Speciale, A. Leone, S. Graffi, G. Masetti","doi":"10.1109/ESSDERC.1997.194428","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194428","url":null,"abstract":"In this work we introduce compact models for both MOS and bipolar transistors used in an advanced smart power technology Deriving the topology of the model on the basis of physical structure and layout geometries we guarantee both physical meaning to model parameters an easy parameters extraction procedure and a similar model structure for parasitic components The models correctly pre dict in uence of parasitic couplings between each component and the collector of the power device showing good agreement with experi mental data","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125291407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Closed-form model of the subhalfmicrometer LDD MOSFET overlap capacitance","authors":"V. Koldyaev, L. Deferm","doi":"10.1109/ESSDERC.1997.194517","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194517","url":null,"abstract":"An accurate closed1orm model of the overlap capacitance is presented. The space charge region at the WD-part of a MOSFET is decomposed into the inner fringing and parallel plate effect components for the non rectangular geometry. The third plate proximity effect and 2D-effects are taken into account. Good agreement between calculated and measured characteristics is fOUnd.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131729477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of non-equilibrium transport and series resistances in 0.1um bulk and SOI MOSFETs","authors":"P. Bricout, E. Augendre, E. Dubois","doi":"10.1109/ESSDERC.1997.194401","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194401","url":null,"abstract":"Impact of non-equilibrium transport on current performances has been investigated by means of device simulation for 0.1μm bulk and SOI MOSFET’s. Although performance degradation due to series resistances is more pronounced than in bulk counterparts, SOI devices take more advantage of velocity overshoot. IIntroduction Optimization of SOI MOSFETs in the 0.1μm regime has been systematically investigated by means of device simulation, including both drift-diffusion and Monte Carlo techniques. Advantages of thin film SOI transistors in terms of short-channeleffect immunity are already known [1]. Moreover, current capability of 0.1μm devices deviates from the behavior predicted by drift-diffusion models, due to non-equilibrium transport.The enhancement of current capability, crucial for high speed applications, has been investigated for fully depleted SOI and bulk structures. The transconductance of both types of devices is also compared with experimental data. IISimulations and results Thin film SOI devices and bulk counterparts have been simulated and the influence of various technological parameters have been investigated (effective channel length L, SOI film thickness tSi, gate oxide thickness tox, buried oxide thickness tBox, bulk or SOI film doping Csub). Results of drift-diffusion simulations are used as an initial solution for Monte Carlo computations, which include non-equilibrium transport. The Monte Carlo simulator uses classical values for scattering coefficients [2]. Scattering at the Si/SiO2 interfaces is treated as a mixture of reflections (82%) and diffusions (18%), in order to obtain the same currents with drift-diffusion and Monte Carlo for a 1μm long bulk transistor (Fig.1). As shown in Fig.2, electron velocity may reach 107cm/s (saturation velocity) even at the source junction, suggesting possible enhancement of current performance due to velocity overshoot in the shorter devices. A comparison of Id-Vd characteristics extracted from drift-diffusion (DD) and Monte Carlo (MC) simulations gives the increase of current directly related to non-stationary transport. At Vg=Vd=2V, this is estimated as +28% for the bulk structure (Fig.3) and +34% for the thin-film SOI device (Fig.4). Non stationary transport also results in transconductance (gm) enhancement as reported in Fig.5. However, the values of gm are well below the maximum of transconductance predicted by the velocity saturation (about 860μS/μm for tOx=4nm). This is confirmed by a comparison with measured values given in Table 1 for devices similar to those investigated in this study. Several factors may explain this limitation: mobility degradation, access resistances, SOI film self heating [4]. According to our study, although non-equilibrium transport significantly enhances current performances, source-drain resistances is still a main limiting factor. IIIConclusion The enhancement of current capability due to non-equilibrium phenomena has been investigated for bulk and SOI MOSFET","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130583347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}