Detailed Matching Analysis of Sub-50 nm-MOS-Transistors

Abstract

The local and global matching of NMOS-transistors with dimensions from W/L = 10 μm/1 μm down to W/L = 1 μm/30 nm is analyzed by a large number of measurements. Results are compared to simulations, verifying the law of area (σV W L T ∝ ⋅ 1 / ) even for smallest geometries. Except the transistors with a gatelength of 1 μm all transistors are structured by a depositionand etchback technique giving an excellent homogeneity and reproducibility in linewidth. Finally proceedings to avoid the increasing mismatch with decreasing channel area will be discussed.