Effects of high temperature on performances and hot-carrier reliability in DC/AC stressed 0.35 um n-MOSFETs

Abstract

!"#$%&!'# The studies on hot-carrier reliability are usually achieved at room temperature (RT) or at low temperature [1,2] as the hot-carrier degradation has generally more impact on the device characteristics at these temperatures than at high temperature (HT). Only few works deal with channel hot-carrier injections and transistor performances at HT in n-MOSFET’s [3,4,5] which must be evaluated for scaling-down technologies as circuits operate over a wide range of temperature. One of the primary reason is the reduced electron mobility and the reduction of the number of high energy carriers able to create damage. The major consequence is that the substrate and gate currents both decrease at HT [4-6] which is mainly caused by an increased mean free path of channel electrons and a reduced channel electric-field at HT. Hence it is expected that the influence of the interface trap generation and the charge trapping in the gate-oxide is reduced at HT. However the degradation of n-MOSFET’s at HT has gained new interests [3] due to the enhanced degradation of the saturation drain current observed in a 0.55-0.65μm LDD CMOS technology. It is generally accepted that the mechanism of interface trap generation is temperature independent using experiments in the 77-295°K range [2] pointing out the effect of the temperature itself on the device characteristics. In this work the impact of HT is studied on the transistor parameters and on the hot-carrier reliability during digital operation.