{"title":"50纳米以下mos晶体管的详细匹配分析","authors":"J. Horstmann, U. Hilleringmann, K. Goser","doi":"10.1109/ESSDERC.1997.194410","DOIUrl":null,"url":null,"abstract":"The local and global matching of NMOS-transistors with dimensions from W/L = 10 μm/1 μm down to W/L = 1 μm/30 nm is analyzed by a large number of measurements. Results are compared to simulations, verifying the law of area (σV W L T ∝ ⋅ 1 / ) even for smallest geometries. Except the transistors with a gatelength of 1 μm all transistors are structured by a depositionand etchback technique giving an excellent homogeneity and reproducibility in linewidth. Finally proceedings to avoid the increasing mismatch with decreasing channel area will be discussed.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Detailed Matching Analysis of Sub-50 nm-MOS-Transistors\",\"authors\":\"J. Horstmann, U. Hilleringmann, K. Goser\",\"doi\":\"10.1109/ESSDERC.1997.194410\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The local and global matching of NMOS-transistors with dimensions from W/L = 10 μm/1 μm down to W/L = 1 μm/30 nm is analyzed by a large number of measurements. Results are compared to simulations, verifying the law of area (σV W L T ∝ ⋅ 1 / ) even for smallest geometries. Except the transistors with a gatelength of 1 μm all transistors are structured by a depositionand etchback technique giving an excellent homogeneity and reproducibility in linewidth. Finally proceedings to avoid the increasing mismatch with decreasing channel area will be discussed.\",\"PeriodicalId\":424167,\"journal\":{\"name\":\"27th European Solid-State Device Research Conference\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"27th European Solid-State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.1997.194410\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"27th European Solid-State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.1997.194410","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
摘要
通过大量的测量分析了从W/L = 10 μm/1 μm到W/L = 1 μm/30 nm的nmos晶体管的局部匹配和全局匹配。将实验结果与仿真结果进行对比，验证了面积定律(σV W L T∝⋅1 /)对最小几何形状的影响。除了栅极长度为1 μm的晶体管外，所有晶体管均采用沉积和蚀刻技术结构，具有良好的均匀性和线宽可重复性。最后将讨论如何避免随信道面积减小而增加的失配。
Detailed Matching Analysis of Sub-50 nm-MOS-Transistors
The local and global matching of NMOS-transistors with dimensions from W/L = 10 μm/1 μm down to W/L = 1 μm/30 nm is analyzed by a large number of measurements. Results are compared to simulations, verifying the law of area (σV W L T ∝ ⋅ 1 / ) even for smallest geometries. Except the transistors with a gatelength of 1 μm all transistors are structured by a depositionand etchback technique giving an excellent homogeneity and reproducibility in linewidth. Finally proceedings to avoid the increasing mismatch with decreasing channel area will be discussed.
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