Statisitcal Analysis for IC-Management

Abstract

Increasing circuit complexity and die area with at the same time decreasing device dimensions render traditional approaches to IC design inadequate. The result is serious risk of suboptimal designs and thus poor performance and/or poor manufacturing yield. New tools are necessary to capture the effects of statistical variability of devices and interconnects on circuit performance. No longer can circuit design be carried out independently of the process design as interactions between the two cannot be neglected. This means redefining the conventional Mead-Conway design style which has served the industry so well in the past. A new design-manufacturing interface is described and a few challenges and solutions are shown.