Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure

Abstract

In this paper, we demonstrate that the sidewall spacer thickness of double polysilicon self-aligned bipolar transistor structure is one of the fundamental limitations in bipolar transistor scaling by using an accurate small signal equivalent circuit. The simulated results show that the maximum fT reduces to half when the sidewall spacer thickness reduces from 0.1μm t o 0.025μm.