双多晶硅自对准双极晶体管结构的局限性

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI:10.1109/ESSDERC.1997.194482

K. Inoh, H. Nii, S. Yoshitomi, C. Yoshino, H. Furuya, H. Nakajima, H. Sugaya, H. Naruse, Y. Katsumata

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引用次数: 4

摘要

本文通过精确的小信号等效电路，证明了双多晶硅自对准双极晶体管结构的侧壁间隔厚度是双极晶体管缩放的基本限制之一。仿真结果表明，当侧壁垫片厚度从0.1μm减小到0.025μm时，最大fT减小到原来的一半。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Limitations of Double Polysilicon Self-Aligned Bipolar Transistor Structure

In this paper, we demonstrate that the sidewall spacer thickness of double polysilicon self-aligned bipolar transistor structure is one of the fundamental limitations in bipolar transistor scaling by using an accurate small signal equivalent circuit. The simulated results show that the maximum fT reduces to half when the sidewall spacer thickness reduces from 0.1μm t o 0.025μm.

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27th European Solid-State Device Research Conference

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