27th European Solid-State Device Research Conference最新文献

{"title":"Correlation between electromigration damage kinetics and microstructure in Cu interconnects","authors":"A. Gladkikhy, M. Karpovski, A. Palevskiz","doi":"10.1109/ESSDERC.1997.194462","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194462","url":null,"abstract":"Strong correlation of the modes of electromigration damage and microstructure is reported for Cu lms It is found that changes in the microstructure may lead to qualitative variation in electromigra tion damage kinetics from the traditional open circuit due to void growth to continuous damage not leading to failure Surface di usion acting simultaneously with grain boundary mass transport is shown to be critical for damage formation Activation energy of electromigra tion mass transport was measured using a modi ed electrical resistance method and it was determined to be eV indicating grain bound ary di usion","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132338666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SiGe gate for highly performant 0.15/0.18um CMOS technology","authors":"T. Skotnicki, P. Bouillon, R. Gwoziecki, A. Halimaoui, C. Mourrain, I. Sagnes, J. Regolini, O. Jouber, M. Paoli, P. Schiavone","doi":"10.1109/ESSDERC.1997.194404","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194404","url":null,"abstract":"This paper reports on the first successful integration of the poly Si.45Ge.55 P+ gate at the transistor level with full 0.18μm CMOS process. Operational devices down to 0.15μm gate length (drawn) are demonstrated. The use of Si.45Ge.55 gate is shown to lead to a substantial decrease in Ioff current (2 decades on the nominal 0.18μm device) resulting from the shift in threshold voltage (220mV). It is shown that this shift in Vth does not alter the transconductance in saturation, which conserves the same high value as that of the lowly-doped channel device with conventional gate. The latter is in contrast with what usually happens when shifting the Vth by increasing channel doping, which then inevitably leads to a degradation in transconductance. These results provide for the first time an experimental foundation to the interest many research labs allocate today to SiGe as gate material. Introduction. Due to the slowing down in performance improvement, much recent research has focused on a radical boosting in current drivability in short-channel CMOS considering such technological break-through solutions as dynamic threshold modulation [1], mid-gap gate [2-7], or vertical MOSFET [8]. In this paper we present the first successful integration of SiGe gate (55% Germanium fraction) with 0.15/0.18μm MOSFETs. As suggested in [6], the principle of mid-gap operation of poly-Ge gates consists in bringing the Fermi level to the edge of the valence band of Ge by P+ doping (single gate for N-and P-MOSFETs), Fig. 1. In this way the gate Fermi level becomes equal to that of the Silicon mid-gap due to the conservation of the electron affinity to Si02 between Si and Ge, and also due to the fact that the forbidden gap of Ge is only half of that of Si. The latter suggests that ideal mid-gap operation is only possible with pure Ge gates. Nevertheless, the 55% Ge fraction gate is, up to our best knowledge, the highest percentage ever succeeded on 0.18 m devices. Process key-points. Heavy ion (4e12at/cm2 at 140keV of As for PMOS and In for NMOS) were used for channel antipunchthrough implants. Because of insufficient shift in Øms with 55% Ge fraction, the NMOS devices received, in addition, a weak dose of a counter-doping As implant for Vth adjustment. As a result, they are buried-channel type, and thus inherit the same well-known drawbacks in subthreshold behaviour as N+ gate PMOSFETs. Therefore, in this paper we will limit our considerations to PMOS devices, considering this approach to be an intermediary step towards full Ge-gate Pand N-MOS integration. The 4nm gate oxide was grown at 750°C in wet ambient. The 120nm thick poly SiGe film was capped with 80nm of poly Si in order to remain as close as possible to conventional poly-Si gate process. The gates were predoped with Boron and patterned using the Phase Shift Mask I-line Lithography. The P+/N junctions were formed by the LDD implant with BF2 of 5e13 at/cm2 at 25keV, followed by the S/D implant (after spacer) of ","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"562 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134101005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stress induced leakage current dependence on oxide thickness, technology and stress level","authors":"A. Scarpa, P. Ries, G. Ghibaudo, A. Paccagnella, G. Pananakakis, J. Brini, G. Ghidini, C. Papadas","doi":"10.1109/ESSDERC.1997.194498","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194498","url":null,"abstract":"","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134294483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of Capacitance Behavior for Short-Channel Accumulation-Mode SOI PMOS Devices","authors":"J. Kuo, K. Su","doi":"10.1109/ESSDERC.1997.194518","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194518","url":null,"abstract":"This paper reports the capacitance behavior of short-channel accumulation­ mode Sal PMOS devices. Based. on the study, compared to the inversion­ mode device, t!l,e accumulation-mode Sal PMOS device has a gradual tran­ sition in GGS from subthreshold to accumulation due to the effect of the buried channel.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115429807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Reflective-mode PDLC Light Valve Display Technology","authors":"P. Cacharelis, J. Frazee, P. Moore, R. Luttrell, R. Flack","doi":"10.1109/ESSDERC.1997.194499","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194499","url":null,"abstract":"A silicon-based display technology was developed using a 0.8 μm EEPROM process flow [1] and a reflective-mode, polymer-dispersed-liquid-crystal (PDLC) cell in order to generate a high resolution light valve. The silicon backplane driver is coupled to the PDLC cell which is mounted directly on the die. Modifications to the EEPROM process frontend and optimization of a 3 layer metal backend were conducted based on the specific requirements of the light valve. The light valves were combined with optical beam-splitting and beamcombining prisms to enable full color projection displays. A prototype projector was assembled to demonstrate the technology approach.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124520520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Frequency Noise Characteristics of Advanced Si and SiGe Bipolar Transistors","authors":"R. Gabl, K. Aufinger, K. Beock, T. Meister","doi":"10.1109/ESSDERC.1997.194484","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194484","url":null,"abstract":"also with Institut fur Materialphysik, Universitat Wien, andLudwig-Boltzmann-Institut fur Festkorperphysik,Wien, AustriaAbstractA comprehensive low- frequency noise characterization of advancedSi and SiGe bipolar transistors is presented. The Si transistors werefound to show higher low-frequency noise than the SiGe devices. Thisis proofed to be a consequence of the oxide grown at the poly-monosilicon interface in the case of the Si devices for the adjustmentof the current gain. The incorporation of Ge in the SiGe HBTs wasfound not to degrade the low-frequency noise performance in com-parison to the Si BTs.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"195 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114737834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A New Method for Verification of MOSFET Models Based on Device Parameter Variations","authors":"C. Kuhn, W. Weber","doi":"10.1109/ESSDERC.1997.194431","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194431","url":null,"abstract":"Statistical variation of the threshold voltage is calculated for both NMOS surface channel and PMOS buried channel devices based on the variation of channel doping. This derivation offers a method for verifying MOSFET parameter models. The -models for the buried channel by S.M.Sze [1], Van der Tol [2] and F.M.Klaassen [3] are tested with the clear result that the model of Klaassen is to be preferred to those of the other research groups.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128338680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tunneling gate oxide MOSFET technology","authors":"H. Momose, S.-i. Nakamura, Y. Katsumata, H. Iwai","doi":"10.1109/ESSDERC.1997.194387","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194387","url":null,"abstract":"Characteristics of direct tunneling gate oxide MOSFETs are described. The effect of the gate leakage current on the MOSFET characteristics be­ comes small as gate length reduces. Extremely high DC and AC perform­ ances were realized using such an ultra-thin oxide down to 1.5 nm. Higher reliability in hot-carrier and TDDB has been also observed.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128472645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"GaN based devices for electronic applications","authors":"M.A. Khan, M. Shur","doi":"10.1109/ESSDERC.1997.194393","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194393","url":null,"abstract":"GaN has a very high breakdown field (the measured value is 1.3 MV/cm (see Gaska et al. (1997) and the expected values are over 5 MV/cm), high peak and saturation velocity (vp ≈ 2.7x10 5 m/s, vs ≈ 1.5x10 m/s predicted by Monte Carlo simulations, see Bhapkar and Shur (1997)), a relatively high electron mobility (up to 800 cm/V-s at room temperature in GaN doped at 10 cm and over 1,500 cm/V-s for two-dimensional electrons at the GaN/AlGaN interface, see Shur et al. (1996)) and a respectable thermal conductivity (comparable to that of Si and three times higher than for GaAs). These properties make GaN and related materials very attractive for applications in electronic devices operating at high temperatures, high power, and/or in a harsh environment.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127531678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RF Moblile Communication Circuits - Comparison of Technologies","authors":"Y. Neuvo","doi":"10.1109/ESSDERC.1997.194375","DOIUrl":"https://doi.org/10.1109/ESSDERC.1997.194375","url":null,"abstract":"This paper will outline the technological challenges faced in mobile telephones, specifically related to RF signal processing. Transceiver architectures are mostly based on the traditional superheterodyne architecture. The architecture involves a variety of components, such as IC’s, filters, oscillators, resonators and other key components. The level of integration is typically low, and the mix of different technologies is wide. In the future new transceiver architectures are needed, which support multimode operation and next generation wireless systems, are software configurable and can benefit from the advancements in CMOS technology.","PeriodicalId":424167,"journal":{"name":"27th European Solid-State Device Research Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127451358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}