SiGe gate for highly performant 0.15/0.18um CMOS technology

Abstract

This paper reports on the first successful integration of the poly Si.45Ge.55 P+ gate at the transistor level with full 0.18μm CMOS process. Operational devices down to 0.15μm gate length (drawn) are demonstrated. The use of Si.45Ge.55 gate is shown to lead to a substantial decrease in Ioff current (2 decades on the nominal 0.18μm device) resulting from the shift in threshold voltage (220mV). It is shown that this shift in Vth does not alter the transconductance in saturation, which conserves the same high value as that of the lowly-doped channel device with conventional gate. The latter is in contrast with what usually happens when shifting the Vth by increasing channel doping, which then inevitably leads to a degradation in transconductance. These results provide for the first time an experimental foundation to the interest many research labs allocate today to SiGe as gate material. Introduction. Due to the slowing down in performance improvement, much recent research has focused on a radical boosting in current drivability in short-channel CMOS considering such technological break-through solutions as dynamic threshold modulation [1], mid-gap gate [2-7], or vertical MOSFET [8]. In this paper we present the first successful integration of SiGe gate (55% Germanium fraction) with 0.15/0.18μm MOSFETs. As suggested in [6], the principle of mid-gap operation of poly-Ge gates consists in bringing the Fermi level to the edge of the valence band of Ge by P+ doping (single gate for N-and P-MOSFETs), Fig. 1. In this way the gate Fermi level becomes equal to that of the Silicon mid-gap due to the conservation of the electron affinity to Si02 between Si and Ge, and also due to the fact that the forbidden gap of Ge is only half of that of Si. The latter suggests that ideal mid-gap operation is only possible with pure Ge gates. Nevertheless, the 55% Ge fraction gate is, up to our best knowledge, the highest percentage ever succeeded on 0.18 m devices. Process key-points. Heavy ion (4e12at/cm2 at 140keV of As for PMOS and In for NMOS) were used for channel antipunchthrough implants. Because of insufficient shift in Øms with 55% Ge fraction, the NMOS devices received, in addition, a weak dose of a counter-doping As implant for Vth adjustment. As a result, they are buried-channel type, and thus inherit the same well-known drawbacks in subthreshold behaviour as N+ gate PMOSFETs. Therefore, in this paper we will limit our considerations to PMOS devices, considering this approach to be an intermediary step towards full Ge-gate Pand N-MOS integration. The 4nm gate oxide was grown at 750°C in wet ambient. The 120nm thick poly SiGe film was capped with 80nm of poly Si in order to remain as close as possible to conventional poly-Si gate process. The gates were predoped with Boron and patterned using the Phase Shift Mask I-line Lithography. The P+/N junctions were formed by the LDD implant with BF2 of 5e13 at/cm2 at 25keV, followed by the S/D implant (after spacer) of 2e15at/cm2 at 25keV of BF2. These implantation steps were followed by an activation flash at 950°C for 30". For comparison, we have also performed a reference split with Phosphorus implanted channel and conventional P+ poly Si gate. Technological and material related results. Fig. 2 shows the 55% SiGe 0.18μm gate patterned on 4nm oxide. Using the SiGe gate (55% Ge), a flat band voltage shift of -350 mV has been obtained, via C-V measurements, Fig. 3. These same CV data allow the gate depletion to be assessed at 13% and 8% for Si and SiGe, respectively. The improvement is attributed to the narrower bandgap and thus better dopant activation in poly-SiGe. The shift in Vth of -220mV resulting from transistor (Lg=0.18μm) measurements, Fig. 4, is lower than that resulting from C-V, probably because of a slightly different SCE, DIBL and fixed charge density. Nevertheless, this shift in Vth allows more than 2 decade reduction in Ioff compared with the poly-Si gate, Fig. 4. The particularly interesting feature of the SiGe gate is that the shift in Vth is obtained without altering the transconductance Gm, Fig. 5, which is something impossible to achieve when shifting Vth by increasing channel doping. Indeed, as seen in Fig. 4, the SiGe-gate As-channel transistor shows almost the same shift in Vth (-0.22V) as the poly-Si gate Ph-channel transistor (-0.27V), both with respect to the poly-Si gate As-channel transistor. At high -Vg, the Gm of the SiGe-gate As-channel transistor comes, however, to the same level as that of the poly-Si gate As-channel transistor, whereas that of the poly-Si gate Ph-channel remains well below, Fig. 5. Electrical performances. As demonstrated in Fig. 6, the SCE and DIBL are well controlled for both poly-Si and poly-SiGe gates down to a 0.15μm gate length (drawn). Fig. 7 shows two families of subthreshold characteristics for short channel poly-SiGe (55% Ge) PMOS transistors with 0.18μm and 0.15μm gate lengths (as-drawn). Worth to be emphasised, is the low Ioff current of roughly 10pA/μm, and the subthreshold slope of 80mV/dec, both measured on 0.18μm transistors at 2.5V drain bias. This excellent subthreshold behaviour is attributed to the shift in Øms due to the poly-SiGe gate and to the beneficial effect of the retrograde As-channel profile. Attractive saturation currents have also been measured on the poly-SiGe gate devices. For the 0.18μm PMOSFET we obtain 315μA/μm at 2.5V, 225μA/μm at 2.0V and 190μA/μm at 1.8V, Fig. 8. Note that the latter corresponds to an Ioff smaller than 10pA/μm, whereas for the conventional Si-gate Ph-channel transistor, the Ion/Ioff trade-off (at 1.8V) reads : Ion=135μA/μm with an Ioff=1pA/μm, which even after normalisation to Ioff=10pA/μm is still much below (155μA/μm) the Ion value relevant to the poly-SiGe gate device (190μA/μm). Reliability issues. In order to verify if the SiGe gate does not involve any new mechanisms of accelerated degradation, we have compared the ageing rates of the two kind (SiGe-gate and Si-gate) of devices. As shown in Fig. 9, the degradation rate is not at all altered by the type of the gate material. The extrapolated device life-time is very comfortable and roughly equal for both types of devices : 1010 years at 1.8V and 10 years at 3.3V, as estimated via a static stress with 10% degradation criterion on reverse (as well as direct) linear drain current measured on nominal 0.18μm device. Conclusions. The first successful development of a 0.18μm MOSFET with poly-Si.45Ge.55 gate has been reported. This new gate material allows more than 2 decade reduction in Ioff without altering the transconductance, a feature impossible to obtain via adjustment of the channel implant. Excellent performances have been obtained with the new devices : Ion of 190μA/μm with an Ioff of less than 10pA/μm. Further improvement is expected via increase in the LDD dose (very low in the studied devices) and via further increase in the Ge fraction. References. 1. C. Wann et.al., IEDM’96 Tech. Dig., pp. 113-116. 2. N. Kistler et al., IEDM’93 Tech. Dig., pp. 727-730. 3. T.-J. King et al., IEDM’90 Tech. Dig., pp. 253-256. 4. D. H. Lee et al., VLSI’96 Tech. Dig., pp. 208-209. 5. T. Ushiki et al., IEDM’96 Tech. Dig., pp. 117-120. 6. T. Skotnicki, ESSDERC’96 Proceedings, pp. 505-514. 7. C. Salm et al., ESSDERC’96 Proceedings, pp. 601-604. 8. L. Risch et al., ESSDERC’95. Proceedings, pp. 101104. N+ poly Si (NMOS) P+ poly Ge (NMOS & PMOS) SiO2 Vth ÷ φms ÷ Φm ⇒ using SiGe gate , Vth NMOS ↑ by Eg/2, and Vth PMOS ↓ by Eg/2 EF Ec