Selectively-Implanted Collector Profile Optimisation for High-Speed Vertical Bipolar Transistors

27th European Solid-State Device Research Conference Pub Date : 1997-09-22 DOI:10.1109/ESSDERC.1997.194427

M. S. Peter, G. Hurkx, C. E. Timmering

引用次数: 4

Abstract

The in uence of a selectively-implanted collector on the performance of a high-speed vertical bipolar transistor has been studied using Design of Experiments methods. Depending on the epilayer thickness two different types of behaviour are found for fT,max and BVCE0.

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高速垂直双极晶体管的选择性植入集电极结构优化

采用实验设计的方法研究了选择性植入集电极对高速垂直双极晶体管性能的影响。根据涂层厚度的不同，fT、max和BVCE0有两种不同的行为类型。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

27th European Solid-State Device Research Conference

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