Junctions design guidelines for 0.18um CMOS

Abstract

In this paper, we report on the influence of junction depth Xj on Ion/Ioff tradeoff. It is shown that short channel effect is almost independent of Xj on condition that Xj does not impact on ∆ L. We demonstrate that it is only via this latter dependence between Xj and ∆ L, that the Vth-vs-Xj implicit dependence comes to play. In addition, our simulation results show that Ion increases significantly with deepening junction (at constant Leff) without degrading Ioff. With this new understanding, junction design guidelines for 0.18um CMOS can be revised. Introduction We present the impact of the junction depth Xj on NMOS performances, by studying a variety of implanted MDD architectures. In order to control the Short Channel Effect (SCE) and the Drain Induced Barrier Lowering (DIBL), it is commonly accepted that Xj should be drastically diminished. On the other hand shallow junctions lead to an increase in parasitic resistance and involve increased process complexity [1-2]. In this paper, it is shown that, thanks to the use of retrograde channel profiles (RCP), only the lateral penetration of the junctions (∆L) is still a critical parameter, whereas the sensitivity to junction depth itself vanishes. Process key-steps The RCP architecture was achieved thanks to Indium implantation. A 40Å gate oxide was grown in 750°C wet ambient. The gates were patterned using the Phase Shift Mask I-Line Lithography, in order to obtain gate lengths down to 0.15μm. Several implantation conditions were tested for the extensions (Tab. 1). The source/drain N+ regions were implanted with Arsenic 2.1015at/cm-2 60keV after 0.1μm spacer formation. The activation was insured by an RTA at 950°C 30", followed by common back-end process. NMOS devices have been characterized by extracting junction dependent parameters, such as parasitic resistance Rs and ∆L. The "Shift and Ratio" method was used [3-4], in order to overcome the limitations of "L array" methods. Analysis of conventional approach 0.18 m gate length NMOS transistors have been fabricated using RCP architecture (Indium 1.1e13cm-2 160keV) and MDD extensions (Arsenic 2e14cm-2 40keV). Despite the strongly doped extensions, these devices do not exhibit punchthrough (Fig. 1), the subthreshold slope is very good (80mV/dec @ Vd=1.8V), and the DIBL is well controlled (80mV). Nevertheless, a low threshold voltage leads to a high Ioff current (13nA/μm), with a Ion current of 530μA/μm, see Fig. 2. Moreover, any reduction in junction depth and/or increase in channel doping level would certainly worsen the Ion current even further, because of the increase in series resistances and/or body effect, respectively. In order to improve this trade-off and establish useful guidelines for junction design, we first analyzed the influence of junction depth Xj on the SCE. When plotted as a function of gate length (Fig. 3), the roll-off (defined as Vth[Lg]-Vth[Lg=5μm]) is increased with increasing junction depth. In contrast, when plotted as a function of the effective length (defined as Lgate-∆L), the roll-off no longer shows any dependence on junction depth Xj (Fig. 5). Similarly, in order to study the tradeoff between SCE and Ion performances, we plotted the intrinsic saturation transconductance Gmisat versus DIBL (Fig. 6), which allows us to correct for the differences in ∆L and parasitic resistances. It is then clear that, for a given DIBL, the Ion intrinsic performances are independent of junction depth Xj. Second step approach Considering that Xj itself is no longer a critical parameter, variations in SCE and DIBL are attributed exclusively to changes in ∆L, in contrast with the common views. Consequently, the solution consists in getting rid of the correlation between Xj and ∆L. In order to test this solution, we have simulated different ideal extensions (Fig. 7) by varying the corresponding depths while keeping the gate overlap constant (i.e. constant ∆L). The extensions were Arsenic-doped (concentration set to 1020at/cm-3) and dopant activation was performed by an RTA at 1000°C 30". The resulting simulated profiles are illustrated in Fig. 8. The Ion current increases from 450μA/μm to 650μA/μm, while Xj (extensions) increases from 2nm to 100nm ( Fig. 9). At the same time, the Ioff current remains almost unchanged (<200pA/μm), this situation holding until bulk punchthrough comes to play. The latter happens when the junction depth escapes from the protection range of the GP doping peak. As shown in Fig. 9, this protective range extends down to 100nm and can be extended even further by increasing either the peak doping or its lateral spread. In practice many solutions exist enabling us to move away the extensions implantation from gate edge. As an example we can mention that consisting in making a short spacer before MDD (Fig. 10) [5], thereby leading to a reduction in ∆L independent of junction depth. Conclusion: We have shown that in the frame of retrograde channel architecture, the junction depth does not have any direct influence on Ioff current. The only important parameter is the effective length Leff. On the other hand, deeper junctions lead to a considerable increase in Ion current. Therefore, the key point in junction design is the control of the lateral spreading of extensions. Summarizing, in contrast with common views, a deep junction gives the best Ion/Ioff compromise, on condition we employ techniques allowing efficient limitation of ∆L. Acknowledgments The authors wish to acknowledge the contributions of GRESSI clean-room and material teams in processing of samples used in this study. References [1] M. Ono et al, IEDM 1993, p. 119. [2] Y. Nakahara et al, VLSI Symp, 1996, p. 174. [3] Y. Taur et al, IEEE EDL Vol. 13, No. 5, May 1992, pp. 267. [4] S. Biesemans et al, VLSI Symp., 1995, p. 166. [5] M. Rodder et al., IEDM 1995, p. 415. Split Conditions MDD1 As 1e14 30keV MDD2 MDD1 + As 1e14 50keV MDD3 MDD1 + As 1e14 70keV MDD4 As 2e14 30keV Tab. 1: MDD implantation conditions 1E-12 1E-11 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03 -0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 V g [V] Id [ A /μ m ] 0.1V Vd=1.8V