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2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)最新文献

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Investigation of memory effect with voltage or current charging pulse bias in MIS structures based on codoped Si-NCs 基于共掺杂si - nc的MIS结构中电压或电流充电脉冲偏置的记忆效应研究
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354749
A. Mazurak, Jakub Jasmski, R. Mroczyński
{"title":"Investigation of memory effect with voltage or current charging pulse bias in MIS structures based on codoped Si-NCs","authors":"A. Mazurak, Jakub Jasmski, R. Mroczyński","doi":"10.1109/ULIS.2018.8354749","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354749","url":null,"abstract":"Co-doped Si-NCs have been introduced into MIS structures with HfOx gate dielectric layers. The fabricated test structures were characterized by means of stress-and-sense measurements in terms of device capacitance, flat-band voltage shift, and retention time. Presented results are promising for applications of Si-NCs in memory structures.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126023194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulation and automated characterisation of optimal load for flexible composite generators based on piezoelectric ZnO nanowires 基于压电ZnO纳米线的柔性复合发电机最优负载仿真与自动化表征
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354762
D. Menin, M. Parmar, R. Tao, P. Oliveira, M. Mouis, L. Selmi, G. Ardila
{"title":"Simulation and automated characterisation of optimal load for flexible composite generators based on piezoelectric ZnO nanowires","authors":"D. Menin, M. Parmar, R. Tao, P. Oliveira, M. Mouis, L. Selmi, G. Ardila","doi":"10.1109/ULIS.2018.8354762","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354762","url":null,"abstract":"This paper reports the experimental and numerical study of flexible piezoelectric transducers made of a thin active composite material (∼3 μm thick) over a thin flexible metallic foil (∼25 μm of stainless steel). The active piezo-layer consists of vertical ZnO nanowires (NWs) embedded into dielectric fillers of different composition. The voltage over a known resistance was measured with an automatic bending setup, and the corresponding power was computed and compared to numerical simulations as a function of load resistance and dielectric matrix in the composite structure. FEM simulations show that the output power can be higher than conventional thin-film devices. These results confirm previous findings and provide important guidelines to optimize flexible piezoelectric transducers for applications as sensors and generators for the Internet of Things. Comparison with a commercial thick-film piezoelectric energy harvester was also made experimentally.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126211071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
TFET-based inverter performance in the presence of traps and localized strain 陷阱和局部应变存在时基于tfet的逆变器性能
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354726
E. Gnani, A. Gnudi, S. Reggiani, B. Baccarani, M. Visciarelli
{"title":"TFET-based inverter performance in the presence of traps and localized strain","authors":"E. Gnani, A. Gnudi, S. Reggiani, B. Baccarani, M. Visciarelli","doi":"10.1109/ULIS.2018.8354726","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354726","url":null,"abstract":"This paper investigates the circuit-level performance of an inverter made by n- and p-type tunnel field-effect transistors (TFETs), integrated on the same InAs/Al0.05Ga0.95Sb technology platform, in the presence of interface traps and localized strain. From 3-D full-quantum simulations, interface traps are found to induce a significant degradation of the voltage gain, noise margin and transient performance. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, although beneficial, is unable to recover the circuit-level performance of the ideal case.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116984413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Potential of thin (∼10 nm) HfO2 ferroelectric FDSOI NCFET for performance enhancement in digital circuits at reduced power consumption 薄(~ 10 nm) HfO2铁电FDSOI NCFET在降低功耗的情况下提高数字电路性能的潜力
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354775
S. Qureshi, S. Mehrotra
{"title":"Potential of thin (∼10 nm) HfO2 ferroelectric FDSOI NCFET for performance enhancement in digital circuits at reduced power consumption","authors":"S. Qureshi, S. Mehrotra","doi":"10.1109/ULIS.2018.8354775","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354775","url":null,"abstract":"A simulation study using thin (∼10 nm) HfO2 PGP FDSOI NCFET based gates is presented. The study has been performed on devices having 20 nm metal gate length with supply voltage varying from 0.5 V to 0.9 V. The circuits studied were 3-stage ring oscillator, NAND-2 and NOR-2 gates. The study showed significant enhancement in the performance in HfO2 FDSOI NCFET based gates at reduced power consumption which is −66% when compared to that of FDSOI MOSFET based gates. The power-delay product of HfO2 FDSOI NCFET based gates was found to be significantly lower (∼24%) in comparison to baseline FDSOI MOSFET based gates. The effect of increasing fan-in and fan-out on the performance of logic gates has also been discussed in the paper.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128115921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Current and shot noise at spin-dependent hopping through magnetic tunnel junctions 磁隧道结中依赖自旋跳变的电流和射散噪声
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354727
V. Sverdlov, S. Selberherr
{"title":"Current and shot noise at spin-dependent hopping through magnetic tunnel junctions","authors":"V. Sverdlov, S. Selberherr","doi":"10.1109/ULIS.2018.8354727","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354727","url":null,"abstract":"Upcoming mass production of energy efficient spin-transfer torque magnetoresistive random access memory will revolutionize modern microelectronics by introducing non-volatility not only for memory but also for logic. However, the pressing issue is to boost the sensing margin by improving the tunneling magnetoresistance ratio. We demonstrate that spin-dependent trap-assisted tunneling in magnetic tunnel junctions can increase the TMR. The influence of spin decoherence and relaxation on the current and shot noise at trap-assisted hopping is investigated.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128408643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effect of Schottky barrier contacts on measured capacitances in tunnel-FETs 隧道场效应管中肖特基势垒触点对测量电容的影响
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354766
A. Farokhnejad, M. Schwarz, M. Graef, F. Horst, B. Iñíguez, F. Lime, A. Kloes
{"title":"Effect of Schottky barrier contacts on measured capacitances in tunnel-FETs","authors":"A. Farokhnejad, M. Schwarz, M. Graef, F. Horst, B. Iñíguez, F. Lime, A. Kloes","doi":"10.1109/ULIS.2018.8354766","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354766","url":null,"abstract":"The influence of Schottky barriers at NiSi2 contacts of Si Planar p-TFETs on Ultrathin Body [1] is analyzed in terms of deviations between measurements, TCAD simulations and a proposed compact model for the intrinsic capacitances in TFETs presented in [2]. A theory for the reason of the deviations for the intrinsic capacitances is evolved and discussed. Additionally, TCAD simulations are performed to support the theory.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"21 1-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123872881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Investigation on built-in BJT in FD-SOI BIMOS FD-SOI BIMOS中内置BJT的研究
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354761
T. Bedecarrats, P. Galy, C. Fenouillet-Béranger, S. Cristoloveanu
{"title":"Investigation on built-in BJT in FD-SOI BIMOS","authors":"T. Bedecarrats, P. Galy, C. Fenouillet-Béranger, S. Cristoloveanu","doi":"10.1109/ULIS.2018.8354761","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354761","url":null,"abstract":"The built-in BJT of a BIMOS fabricated in 28nm UTBB FD-SOI high-k metal technology from ST Microelectronics is investigated in common-emitter mode and in MOSFET off-state. In the weak VBE regime, field-effects dominate, generating a negative base current and making the current gain β0 meaningless. For Vbe high enough, the BJT works normally but with and a very low gain.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127984296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Simulation study on Z2FET scalability, process optimization and their impact on performance Z2FET可扩展性、工艺优化及其对性能影响的仿真研究
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354340
M. Duan, F. Adamu-Lema, C. Navarro, F. Gamiz, A. Asenov
{"title":"Simulation study on Z2FET scalability, process optimization and their impact on performance","authors":"M. Duan, F. Adamu-Lema, C. Navarro, F. Gamiz, A. Asenov","doi":"10.1109/ULIS.2018.8354340","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354340","url":null,"abstract":"Memory technology requires high density, large volume memory arrays in the limited chip real estate. Z2FET memory architecture has demonstrated advantages for CMOS technology implementation including compatibility and scalability, novel capacitor-less memory action, area reduction, and sharp switching characteristics. As a candidate of e-DRAM applications [1-4], minimizing cell dimensions is one of the key targets in order to deliver Z2FET competitive advantage in memory technology design and applications. The cell area is mainly determined by the Z2FET length and width. Therefore, the scaling study the Z2FET length is crucial in achieving high-density storage solutions.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127074277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-frequency noise in surface-treated AlGaN/GaN HFETs 表面处理AlGaN/GaN hfet中的低频噪声
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354738
Ki-Sik Im, Jun-Hyeok Lee, Jung-Hee Lee, C. Theodorou, G. Ghibaudo, S. Cristoloveanu
{"title":"Low-frequency noise in surface-treated AlGaN/GaN HFETs","authors":"Ki-Sik Im, Jun-Hyeok Lee, Jung-Hee Lee, C. Theodorou, G. Ghibaudo, S. Cristoloveanu","doi":"10.1109/ULIS.2018.8354738","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354738","url":null,"abstract":"We investigated the 1/f noise generation mechanism in surface-treated AlGaN/GaN heterojunction field-effect transistors (HFETs) with different gate length and gate-to-drain distance (Lgd). From the normalized drain current power spectral density (PSD) SIdId2 versus Id, the AlGaN/GaN HFET with shorter gate length exhibited the Hooge mobility fluctuation (HMF) in subthreshold region and the carrier number fluctuation (CNF) above threshold gate voltage. On the other hand, the HFET with longer gate of 20 μm followed the correlated mobility fluctuation (CMF), irrespective of the gate bias. The extracted trap density (Nt) in the HFET with shorter gate length was noticeably less than that in the HFET with longer length. The input gate voltage power spectral density (PSD) proves that the HFET with shorter gate length suffers from higher interface roughness scattering.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130597939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Dickson rectifier for RF energy harvesting in 28 nm FD-SOI technology 28nm FD-SOI技术中射频能量收集的Dickson整流器设计
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) Pub Date : 2018-03-01 DOI: 10.1109/ULIS.2018.8354751
M. Awad, P. Benech, J. Duchamp
{"title":"Design of Dickson rectifier for RF energy harvesting in 28 nm FD-SOI technology","authors":"M. Awad, P. Benech, J. Duchamp","doi":"10.1109/ULIS.2018.8354751","DOIUrl":"https://doi.org/10.1109/ULIS.2018.8354751","url":null,"abstract":"In the context of the radio frequency energy harvesting, RF-DC converter based on a one stage Dickson voltage rectifier has been studied and realized in 28 nm FD-SOI technology. After the analysis of the operating constraints of the circuit, a choice was made on the N-low threshold voltage transistor (NLVT). Moreover, the back gate polarization (BGP) effect, on circuit performance, has been analyzed and a dynamic BGP is proposed which improve rectifier performance.","PeriodicalId":383788,"journal":{"name":"2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)","volume":"53 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120816767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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