TFET-based inverter performance in the presence of traps and localized strain

This paper investigates the circuit-level performance of an inverter made by n- and p-type tunnel field-effect transistors (TFETs), integrated on the same InAs/Al0.05Ga0.95Sb technology platform, in the presence of interface traps and localized strain. From 3-D full-quantum simulations, interface traps are found to induce a significant degradation of the voltage gain, noise margin and transient performance. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, although beneficial, is unable to recover the circuit-level performance of the ideal case.